##
## This file is part of the libsigrokdecode project.
##
-## Copyright (C) 2011-2013 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# UART protocol decoder
-
import sigrokdecode as srd
+'''
+OUTPUT_PYTHON format:
+
+UART packet:
+[<packet-type>, <rxtx>, <packet-data>]
+
+This is the list of <packet-type>s and their respective <packet-data>:
+ - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
+ - 'DATA': The data is the (integer) value of the UART data. Valid values
+ range from 0 to 512 (as the data can be up to 9 bits in size).
+ - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
+ - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
+ - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
+ - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
+ - 'PARITY ERROR': The data is a tuple with two entries. The first one is
+ the expected parity value, the second is the actual parity value.
+ - TODO: Frame error?
+
+The <rxtx> field is 0 for RX packets, 1 for TX packets.
+'''
+
# Used for differentiating between the two data directions.
RX = 0
TX = 1
# TODO: Options to invert the signal(s).
}
annotations = [
- ['Data', 'UART data'],
+ ['rx-data', 'UART RX data'],
+ ['tx-data', 'UART TX data'],
+ ['start-bits', 'UART start bits'],
+ ['parity-bits', 'UART parity bits'],
+ ['stop-bits', 'UART stop bits'],
+ ['warnings', 'Warnings'],
]
+ binary = (
+ ('rx', 'RX dump'),
+ ('tx', 'TX dump'),
+ ('rxtx', 'RX/TX dump'),
+ )
def putx(self, rxtx, data):
s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
def putp(self, data):
s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_proto, data)
+ self.put(s - halfbit, s + halfbit, self.out_python, data)
+
+ def putbin(self, rxtx, data):
+ s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
+ self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data)
def __init__(self, **kwargs):
+ self.samplerate = None
self.samplenum = 0
self.frame_start = [-1, -1]
self.startbit = [-1, -1]
self.oldbit = [1, 1]
self.oldpins = [1, 1]
- def start(self, metadata):
- self.samplerate = metadata['samplerate']
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_bin = self.register(srd.OUTPUT_BINARY)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
- # The width of one UART bit in number of samples.
- self.bit_width = \
- float(self.samplerate) / float(self.options['baudrate'])
-
- def report(self):
- pass
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value;
+ # The width of one UART bit in number of samples.
+ self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
# Return true if we reached the middle of the desired bit, false otherwise.
def reached_bit(self, rxtx, bitnum):
self.state[rxtx] = 'GET DATA BITS'
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([0, ['Start bit', 'Start', 'S']])
+ self.putg([2, ['Start bit', 'Start', 'S']])
def get_data_bits(self, rxtx, signal):
# Skip samples until we're in the middle of the desired data bit.
self.putp(['DATA', rxtx, self.databyte[rxtx]])
- s = 'RX: ' if (rxtx == RX) else 'TX: '
b, f = self.databyte[rxtx], self.options['format']
if f == 'ascii':
- self.putx(rxtx, [0, [s + chr(b)]])
+ c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
+ self.putx(rxtx, [rxtx, [c]])
elif f == 'dec':
- self.putx(rxtx, [0, [s + str(b)]])
+ self.putx(rxtx, [rxtx, [str(b)]])
elif f == 'hex':
- self.putx(rxtx, [0, [s + hex(b)[2:]]])
+ self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]])
elif f == 'oct':
- self.putx(rxtx, [0, [s + oct(b)[2:]]])
+ self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
elif f == 'bin':
- self.putx(rxtx, [0, [s + bin(b)[2:]]])
+ self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
else:
raise Exception('Invalid data format option: %s' % f)
+ self.putbin(rxtx, (rxtx, bytes([b])))
+ self.putbin(rxtx, (2, bytes([b])))
+
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
if self.options['parity_type'] == 'none':
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
self.databyte[rxtx], self.options['num_data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([0, ['Parity bit', 'Parity', 'P']])
+ self.putg([3, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([0, ['Parity error', 'Parity err', 'PE']])
+ self.putg([5, ['Parity error', 'Parity err', 'PE']])
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
+ self.putg([5, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([0, ['Stop bit', 'Stop', 'T']])
+ self.putg([4, ['Stop bit', 'Stop', 'T']])
def decode(self, ss, es, data):
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
# TODO: Either RX or TX could be omitted (optional probe).
for (self.samplenum, pins) in data:
projects / libsigrokdecode.git / blobdiff