uart: Add trekstor_ebr30_a test case.

[libsigrokdecode.git] / decoders / uart / pd.py

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index c3d1b62dbc5849f16fc4c5cf91f322cf8dfd36f9..00be94bdd1b50da1a501a8d066716c992305ab85 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# UART protocol decoder
-
 import sigrokdecode as srd
 
 '''
@@ -97,12 +95,12 @@ class Decoder(srd.Decoder):
         # TODO: Options to invert the signal(s).
     }
     annotations = [
-        ['RX data', 'UART RX data'],
-        ['TX data', 'UART TX data'],
-        ['Start bits', 'UART start bits'],
-        ['Parity bits', 'UART parity bits'],
-        ['Stop bits', 'UART stop bits'],
-        ['Warnings', 'Warnings'],
+        ['rx-data', 'UART RX data'],
+        ['tx-data', 'UART TX data'],
+        ['start-bits', 'UART start bits'],
+        ['parity-bits', 'UART parity bits'],
+        ['stop-bits', 'UART stop bits'],
+        ['warnings', 'Warnings'],
     ]
     binary = (
         ('rx', 'RX dump'),
@@ -232,7 +230,7 @@ class Decoder(srd.Decoder):
 
         b, f = self.databyte[rxtx], self.options['format']
         if f == 'ascii':
-            c = chr(b) if chr(b).isprintable() else '[%02X]' % b
+            c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
             self.putx(rxtx, [rxtx, [c]])
         elif f == 'dec':
             self.putx(rxtx, [rxtx, [str(b)]])