-
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
-
- def report(self):
- return 'SPI: %d bytes received' % self.bytesreceived
-
- def decode(self, ss, es, data):
- # TODO: Either MISO or MOSI could be optional. CS# is optional.
- for (self.samplenum, pins) in data:
-
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins, (miso, mosi, sck, cs) = pins, pins
-
- if self.oldcs != cs:
- # Send all CS# pin value changes.
- self.put(self.samplenum, self.samplenum, self.out_proto,
- ['CS-CHANGE', self.oldcs, cs])
- self.put(self.samplenum, self.samplenum, self.out_ann,
- [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
- self.oldcs = cs
-
- # Ignore sample if the clock pin hasn't changed.
- if sck == self.oldsck:
- continue
-
- self.oldsck = sck
-
- # Sample data on rising/falling clock edge (depends on mode).
- mode = spi_mode[self.options['cpol'], self.options['cpha']]
- if mode == 0 and sck == 0: # Sample on rising clock edge
- continue
- elif mode == 1 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 2 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 3 and sck == 0: # Sample on rising clock edge
- continue
-
- # If this is the first bit, save its sample number.
- if self.bitcount == 0:
- self.start_sample = self.samplenum
+ self.have_cs = None
+ self.have_miso = None
+ self.have_mosi = None
+ self.state = 'IDLE'
+
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
+
+ def start(self):
+ self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_bitrate = self.register(srd.OUTPUT_META,
+ meta=(int, 'Bitrate', 'Bitrate during transfers'))
+
+ def putpw(self, data):
+ self.put(self.startsample, self.samplenum, self.out_proto, data)
+
+ def putw(self, data):
+ self.put(self.startsample, self.samplenum, self.out_ann, data)
+
+ def handle_bit(self, miso, mosi, sck, cs):
+ # If this is the first bit, save its sample number.
+ if self.bitcount == 0:
+ self.startsample = self.samplenum
+ if self.have_cs: