+ # Ignore sample if the clock pin hasn't changed.
+ if sck == self.oldsck:
+ return
+
+ self.oldsck = sck
+
+ # Sample data on rising/falling clock edge (depends on mode).
+ mode = spi_mode[self.options['cpol'], self.options['cpha']]
+ if mode == 0 and sck == 0: # Sample on rising clock edge
+ return
+ elif mode == 1 and sck == 1: # Sample on falling clock edge
+ return
+ elif mode == 2 and sck == 1: # Sample on falling clock edge
+ return
+ elif mode == 3 and sck == 0: # Sample on rising clock edge
+ return
+
+ # Found the correct clock edge, now get the SPI bit(s).
+ self.handle_bit(miso, mosi, sck, cs)
+
+ def decode(self, ss, es, data):
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
+ # Either MISO or MOSI can be omitted (but not both). CS# is optional.
+ for (self.samplenum, pins) in data:
+
+ # Ignore identical samples early on (for performance reasons).
+ if self.oldpins == pins:
+ continue
+ self.oldpins, (sck, miso, mosi, cs) = pins, pins
+ self.have_miso = (miso in (0, 1))
+ self.have_mosi = (mosi in (0, 1))
+ self.have_cs = (cs in (0, 1))
+
+ # State machine.
+ if self.state == 'IDLE':
+ self.find_clk_edge(miso, mosi, sck, cs)
+ else:
+ raise Exception('Invalid state: %s' % self.state)