## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
-## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# SPI protocol decoder
-
import sigrokdecode as srd
+'''
+Protocol output format:
+
+SPI packet:
+[<cmd>, <data1>, <data2>]
+
+Commands:
+ - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
+ The data is _usually_ 8 bits (but can also be fewer or more bits).
+ Both data items are Python numbers (not strings), or None if the respective
+ probe was not supplied.
+ - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
+ Both data items are Python numbers (0/1), not strings.
+
+Examples:
+ ['CS-CHANGE', 1, 0]
+ ['DATA', 0xff, 0x3a]
+ ['DATA', 0x65, 0x00]
+ ['DATA', 0xa8, None]
+ ['DATA', None, 0x55]
+ ['CS-CHANGE', 0, 1]
+'''
+
# Key: (CPOL, CPHA). Value: SPI mode.
# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
inputs = ['logic']
outputs = ['spi']
probes = [
+ {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+ ]
+ optional_probes = [
{'id': 'miso', 'name': 'MISO',
- 'desc': 'SPI MISO line (Master in, slave out)'},
+ 'desc': 'SPI MISO line (master in, slave out)'},
{'id': 'mosi', 'name': 'MOSI',
- 'desc': 'SPI MOSI line (Master out, slave in)'},
- {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
- {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
+ 'desc': 'SPI MOSI line (master out, slave in)'},
+ {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
]
- optional_probes = [] # TODO
options = {
'cs_polarity': ['CS# polarity', 'active-low'],
'cpol': ['Clock polarity', 0],
'format': ['Data format', 'hex'],
}
annotations = [
- ['Data', 'SPI data'],
- ['Warnings', 'Human-readable warnings'],
+ ['miso-data', 'MISO SPI data'],
+ ['mosi-data', 'MOSI SPI data'],
+ ['warnings', 'Human-readable warnings'],
]
def __init__(self):
+ self.samplerate = None
self.oldsck = 1
self.bitcount = 0
self.mosidata = 0
self.misodata = 0
- self.bytesreceived = 0
self.startsample = -1
self.samplenum = -1
self.cs_was_deasserted_during_data_word = 0
self.oldcs = -1
self.oldpins = None
+ self.have_cs = None
+ self.have_miso = None
+ self.have_mosi = None
+ self.state = 'IDLE'
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
- def report(self):
- return 'SPI: %d bytes received' % self.bytesreceived
+ def start(self):
+ self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_bitrate = self.register(srd.OUTPUT_META,
+ meta=(int, 'Bitrate', 'Bitrate during transfers'))
def putpw(self, data):
self.put(self.startsample, self.samplenum, self.out_proto, data)
def putw(self, data):
self.put(self.startsample, self.samplenum, self.out_ann, data)
- def decode(self, ss, es, data):
- # TODO: Either MISO or MOSI could be optional. CS# is optional.
- for (self.samplenum, pins) in data:
-
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins, (miso, mosi, sck, cs) = pins, pins
-
- if self.oldcs != cs:
- # Send all CS# pin value changes.
- self.put(self.samplenum, self.samplenum, self.out_proto,
- ['CS-CHANGE', self.oldcs, cs])
- self.oldcs = cs
-
- # Ignore sample if the clock pin hasn't changed.
- if sck == self.oldsck:
- continue
-
- self.oldsck = sck
-
- # Sample data on rising/falling clock edge (depends on mode).
- mode = spi_mode[self.options['cpol'], self.options['cpha']]
- if mode == 0 and sck == 0: # Sample on rising clock edge
- continue
- elif mode == 1 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 2 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 3 and sck == 0: # Sample on rising clock edge
- continue
-
- # If this is the first bit, save its sample number.
- if self.bitcount == 0:
- self.startsample = self.samplenum
+ def handle_bit(self, miso, mosi, sck, cs):
+ # If this is the first bit, save its sample number.
+ if self.bitcount == 0:
+ self.startsample = self.samplenum
+ if self.have_cs:
active_low = (self.options['cs_polarity'] == 'active-low')
deasserted = cs if active_low else not cs
if deasserted:
self.cs_was_deasserted_during_data_word = 1
- ws = self.options['wordsize']
+ ws = self.options['wordsize']
- # Receive MOSI bit into our shift register.
+ # Receive MOSI bit into our shift register.
+ if self.have_mosi:
if self.options['bitorder'] == 'msb-first':
self.mosidata |= mosi << (ws - 1 - self.bitcount)
else:
self.mosidata |= mosi << self.bitcount
- # Receive MISO bit into our shift register.
+ # Receive MISO bit into our shift register.
+ if self.have_miso:
if self.options['bitorder'] == 'msb-first':
self.misodata |= miso << (ws - 1 - self.bitcount)
else:
self.misodata |= miso << self.bitcount
- self.bitcount += 1
+ self.bitcount += 1
- # Continue to receive if not enough bits were received, yet.
- if self.bitcount != ws:
- continue
+ # Continue to receive if not enough bits were received, yet.
+ if self.bitcount != ws:
+ return
- self.putpw(['DATA', self.mosidata, self.misodata])
- self.putw([0, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
- self.misodata)]])
+ si = self.mosidata if self.have_mosi else None
+ so = self.misodata if self.have_miso else None
- if self.cs_was_deasserted_during_data_word:
- self.putw([1, ['CS# was deasserted during this data word!']])
+ # Pass MOSI and MISO to the next PD up the stack.
+ self.putpw(['DATA', si, so])
- # Reset decoder state.
- self.mosidata = 0
- self.misodata = 0
+ # Annotations.
+ if self.have_miso:
+ self.putw([0, ['%02X' % self.misodata]])
+ if self.have_mosi:
+ self.putw([1, ['%02X' % self.mosidata]])
+
+ # Meta bitrate.
+ elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
+ bitrate = int(1 / elapsed * self.options['wordsize'])
+ self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
+
+ if self.have_cs and self.cs_was_deasserted_during_data_word:
+ self.putw([2, ['CS# was deasserted during this data word!']])
+
+ # Reset decoder state.
+ self.misodata = 0 if self.have_miso else None
+ self.mosidata = 0 if self.have_mosi else None
+ self.bitcount = 0
+
+ def find_clk_edge(self, miso, mosi, sck, cs):
+ if self.have_cs and self.oldcs != cs:
+ # Send all CS# pin value changes.
+ self.put(self.samplenum, self.samplenum, self.out_proto,
+ ['CS-CHANGE', self.oldcs, cs])
+ self.oldcs = cs
+ # Reset decoder state when CS# changes (and the CS# pin is used).
+ self.misodata = 0 if self.have_miso else None
+ self.mosidata = 0 if self.have_mosi else None
self.bitcount = 0
- # Keep stats for summary.
- self.bytesreceived += 1
+ # Ignore sample if the clock pin hasn't changed.
+ if sck == self.oldsck:
+ return
+
+ self.oldsck = sck
+
+ # Sample data on rising/falling clock edge (depends on mode).
+ mode = spi_mode[self.options['cpol'], self.options['cpha']]
+ if mode == 0 and sck == 0: # Sample on rising clock edge
+ return
+ elif mode == 1 and sck == 1: # Sample on falling clock edge
+ return
+ elif mode == 2 and sck == 1: # Sample on falling clock edge
+ return
+ elif mode == 3 and sck == 0: # Sample on rising clock edge
+ return
+
+ # Found the correct clock edge, now get the SPI bit(s).
+ self.handle_bit(miso, mosi, sck, cs)
+
+ def decode(self, ss, es, data):
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
+ # Either MISO or MOSI can be omitted (but not both). CS# is optional.
+ for (self.samplenum, pins) in data:
+
+ # Ignore identical samples early on (for performance reasons).
+ if self.oldpins == pins:
+ continue
+ self.oldpins, (sck, miso, mosi, cs) = pins, pins
+ self.have_miso = (miso in (0, 1))
+ self.have_mosi = (mosi in (0, 1))
+ self.have_cs = (cs in (0, 1))
+
+ # State machine.
+ if self.state == 'IDLE':
+ self.find_clk_edge(miso, mosi, sck, cs)
+ else:
+ raise Exception('Invalid state: %s' % self.state)
projects / libsigrokdecode.git / blobdiff