Add a few missing probe-names.

[libsigrokdecode.git] / decoders / rtc8564 / pd.py

diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py
index bf5d4b6c731bce2afc7cb3b58df858fd32401a9d..728cae6500c98f45e2e51be98863f40a679b8a63 100644 (file)
--- a/decoders/rtc8564/pd.py
+++ b/decoders/rtc8564/pd.py
@@ -1,5 +1,5 @@
 ##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
 ##
 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# Epson RTC-8564 JE/NB protocol decoder
-
 import sigrokdecode as srd
 
 # Return the specified BCD number (max. 8 bits) as integer.
@@ -37,13 +35,13 @@ class Decoder(srd.Decoder):
     outputs = ['rtc8564']
     probes = []
     optional_probes = [
-        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'TODO.'},
-        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'TODO.'},
-        {'id': 'int', 'name': 'INT#', 'desc': 'TODO.'},
+        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
+        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
+        {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
     ]
     options = {}
     annotations = [
-        ['Text', 'Human-readable text'],
+        ['text', 'Human-readable text'],
     ]
 
     def __init__(self, **kwargs):
@@ -55,12 +53,9 @@ class Decoder(srd.Decoder):
         self.months = -1
         self.years = -1
 
-    def start(self, metadata):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'rtc8564')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'rtc8564')
-
-    def report(self):
-        pass
+    def start(self):
+        # self.out_python = self.register(srd.OUTPUT_PYTHON)
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
@@ -147,12 +142,12 @@ class Decoder(srd.Decoder):
     def decode(self, ss, es, data):
         cmd, databyte = data
 
-        # Store the start/end samples of this I2C packet.
+        # Store the start/end samples of this I²C packet.
         self.ss, self.es = ss, es
 
         # State machine.
         if self.state == 'IDLE':
-            # Wait for an I2C START condition.
+            # Wait for an I²C START condition.
             if cmd != 'START':
                 return
             self.state = 'GET SLAVE ADDR'
@@ -212,5 +207,5 @@ class Decoder(srd.Decoder):
             else:
                 pass # TODO?
         else:
-            raise Exception('Invalid state: %d' % self.state)
+            raise Exception('Invalid state: %s' % self.state)