microwire: Drop some trailing whitespace.

[libsigrokdecode.git] / decoders / microwire / pd.py

diff --git a/decoders/microwire/pd.py b/decoders/microwire/pd.py
index 6064de764b74e7bbf79c7d70ee556bf42fdbfc1b..2724c78850b142a1fdabc4bb2fe651c602fbc8db 100644 (file)
--- a/decoders/microwire/pd.py
+++ b/decoders/microwire/pd.py
@@ -29,7 +29,7 @@ Packet:
   'so': SO bit,
  }, ...]
 
-Since address and word size are variable, a list of all bits in each packet 
+Since address and word size are variable, a list of all bits in each packet
 need to be output. Since Microwire is a synchronous protocol with separate
 input and output lines (SI and SO) they are provided together, but because
 Microwire is half-duplex only the SI or SO bits will be considered at once.
@@ -56,14 +56,15 @@ class Decoder(srd.Decoder):
         ('start-bit', 'Start bit'),
         ('si-bit', 'SI bit'),
         ('so-bit', 'SO bit'),
-        ('status-check', 'Status check'),
+        ('status-check-ready', 'Status check ready'),
+        ('status-check-busy', 'Status check busy'),
         ('warning', 'Warning'),
     )
     annotation_rows = (
         ('si-bits', 'SI bits', (0, 1)),
         ('so-bits', 'SO bits', (2,)),
-        ('status', 'Status', (3,)),
-        ('warnings', 'Warnings', (4,)),
+        ('status', 'Status', (3, 4)),
+        ('warnings', 'Warnings', (5,)),
     )
 
     def start(self):
@@ -76,7 +77,7 @@ class Decoder(srd.Decoder):
             cs, sk, si, so = self.wait({0: 'r'})
             if sk:
                 self.put(self.samplenum, self.samplenum, self.out_ann,
-                     [4, ['Clock should be low on start',
+                     [5, ['Clock should be low on start',
                      'Clock high on start', 'Clock high', 'SK high']])
                 sk = 0 # Enforce correct state for correct clock handling.
                 # Because we don't know if this is bit communication or a
@@ -88,10 +89,8 @@ class Decoder(srd.Decoder):
                 packet.append({'samplenum': self.samplenum,
                               'matched': self.matched,
                               'cs': cs, 'sk': sk, 'si': si, 'so': so})
-                if sk == 0:
-                    cs, sk, si, so = self.wait([{0: 'l'}, {1: 'r'}, {3: 'e'}])
-                else:
-                    cs, sk, si, so = self.wait([{0: 'l'}, {1: 'f'}, {3: 'e'}])
+                edge = 'r' if sk == 0 else 'f'
+                cs, sk, si, so = self.wait([{0: 'l'}, {1: edge}, {3: 'e'}])
             # Save last change.
             packet.append({'samplenum': self.samplenum,
                           'matched': self.matched,
@@ -120,16 +119,16 @@ class Decoder(srd.Decoder):
                     if len(change['matched']) > 2 and change['matched'][2]:
                         if bit_so == 0 and change['so']:
                             # Rising edge Busy -> Ready.
-                            self.put(start_samplenum, change['samplenum'], 
-                                     self.out_ann, [3, ['Busy', 'B']])
+                            self.put(start_samplenum, change['samplenum'],
+                                     self.out_ann, [4, ['Busy', 'B']])
                         start_samplenum = change['samplenum']
                         bit_so = change['so']
                 # Put last state.
                 if bit_so == 0:
-                    self.put(start_samplenum, packet[-1]['samplenum'], 
-                             self.out_ann, [3, ['Busy', 'B']])
+                    self.put(start_samplenum, packet[-1]['samplenum'],
+                             self.out_ann, [4, ['Busy', 'B']])
                 else:
-                    self.put(start_samplenum, packet[-1]['samplenum'], 
+                    self.put(start_samplenum, packet[-1]['samplenum'],
                              self.out_ann, [3, ['Ready', 'R']])
             else:
                 # Bit communication.
@@ -150,7 +149,7 @@ class Decoder(srd.Decoder):
                                     if bit_si == 0: # Start bit missing.
                                         self.put(bit_start, change['samplenum'],
                                                  self.out_ann,
-                                                 [4, ['Start bit not high',
+                                                 [5, ['Start bit not high',
                                                  'Start bit low']])
                                     else:
                                         self.put(bit_start, change['samplenum'],