All PDs: More consistent names for ss/es variables.

[libsigrokdecode.git] / decoders / ds1307 / pd.py

diff --git a/decoders/ds1307/pd.py b/decoders/ds1307/pd.py
index d9aa3d5805f1fd1ed9bddc741bb9d788b03f3647..b784b6dd225bfcb6e51a4607cd0ad6d70bfa10c3 100644 (file)
--- a/decoders/ds1307/pd.py
+++ b/decoders/ds1307/pd.py
@@ -44,6 +44,8 @@ rates = {
     0b11: '32768kHz',
 }
 
+DS1307_I2C_ADDRESS = 0x68
+
 def regs_and_bits():
     l = [('reg-' + r.lower(), r + ' register') for r in regs]
     l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
@@ -67,11 +69,13 @@ class Decoder(srd.Decoder):
         ('write-datetime', 'Write date/time'),
         ('reg-read', 'Register read'),
         ('reg-write', 'Register write'),
+        ('warnings', 'Warnings'),
     )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(9, 24))),
         ('regs', 'Registers', tuple(range(9))),
         ('date-time', 'Date/time', (24, 25, 26, 27)),
+        ('warnings', 'Warnings', (28,)),
     )
 
     def __init__(self, **kwargs):
@@ -180,14 +184,25 @@ class Decoder(srd.Decoder):
         d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
             days_of_week[self.days - 1], self.date, self.months,
             self.years, self.hours, self.minutes, self.seconds)
-        self.put(self.block_start_sample, self.es, self.out_ann,
+        self.put(self.ss_block, self.es, self.out_ann,
                  [cls, ['%s date/time: %s' % (rw, d)]])
 
     def handle_reg(self, b):
         r = self.reg if self.reg < 8 else 0x3f
         fn = getattr(self, 'handle_reg_0x%02x' % r)
         fn(b)
+        # Honor address auto-increment feature of the DS1307. When the
+        # address reaches 0x3f, it will wrap around to address 0.
         self.reg += 1
+        if self.reg > 0x3f:
+            self.reg = 0
+
+    def is_correct_chip(self, addr):
+        if addr == DS1307_I2C_ADDRESS:
+            return True
+        self.put(self.ss_block, self.es, self.out_ann,
+                 [28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]])
+        return False
 
     def decode(self, ss, es, data):
         cmd, databyte = data
@@ -207,12 +222,14 @@ class Decoder(srd.Decoder):
             if cmd != 'START':
                 return
             self.state = 'GET SLAVE ADDR'
-            self.block_start_sample = ss
+            self.ss_block = ss
         elif self.state == 'GET SLAVE ADDR':
             # Wait for an address write operation.
-            # TODO: We should only handle packets to the RTC slave (0x68).
             if cmd != 'ADDRESS WRITE':
                 return
+            if not self.is_correct_chip(databyte):
+                self.state = 'IDLE'
+                return
             self.state = 'GET REG ADDR'
         elif self.state == 'GET REG ADDR':
             # Wait for a data write (master selects the slave register).
@@ -233,10 +250,12 @@ class Decoder(srd.Decoder):
                 self.state = 'IDLE'
         elif self.state == 'READ RTC REGS':
             # Wait for an address read operation.
-            # TODO: We should only handle packets to the RTC slave (0x68).
-            if cmd == 'ADDRESS READ':
-                self.state = 'READ RTC REGS2'
+            if cmd != 'ADDRESS READ':
+                return
+            if not self.is_correct_chip(databyte):
+                self.state = 'IDLE'
                 return
+            self.state = 'READ RTC REGS2'
         elif self.state == 'READ RTC REGS2':
             if cmd == 'DATA READ':
                 self.handle_reg(databyte)