instance: return SRD_ERR_TERM_REQ when execution shall terminate

[libsigrokdecode.git] / decoders / avr_pdi / pd.py

diff --git a/decoders/avr_pdi/pd.py b/decoders/avr_pdi/pd.py
index 1568fdf4b336a5bf5bd95ef35a94e4614fb1f51f..7fedbbdfe18e4e18b8447134adc271591c143d21 100644 (file)
--- a/decoders/avr_pdi/pd.py
+++ b/decoders/avr_pdi/pd.py
@@ -112,7 +112,7 @@ class PDI:
     }
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'avr_pdi'
     name = 'AVR PDI'
     longname = 'Atmel Program and Debug Interface'
@@ -154,10 +154,10 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
-        # Detect input changes and clock edges.
-        self.prev_pins = None
-        self.prev_clock = None
         self.clear_state()
 
     def clear_state(self):
@@ -546,12 +546,7 @@ class Decoder(srd.Decoder):
         # Reset internal state for the next frame.
         self.bits = []
 
-    def find_clk_edge(self, samplenum, clock_pin, data_pin):
-        # Ignore the sample if the clock pin has not changed.
-        if clock_pin == self.prev_clock:
-            return
-        self.prev_clock = clock_pin
-
+    def handle_clk_edge(self, clock_pin, data_pin):
         # Sample the data line on rising clock edges. Always, for TX and for
         # RX bytes alike.
         if clock_pin == 1:
@@ -564,7 +559,7 @@ class Decoder(srd.Decoder):
         # periods (avoid interpreting the DATA line when the "enabled" state
         # has not yet been determined).
         self.ss_last_fall = self.ss_curr_fall
-        self.ss_curr_fall = samplenum
+        self.ss_curr_fall = self.samplenum
         if self.ss_last_fall is None:
             return
 
@@ -573,14 +568,6 @@ class Decoder(srd.Decoder):
         bit_val = self.data_sample
         self.handle_bits(bit_ss, bit_es, bit_val)
 
-    def decode(self, ss, es, data):
-        for samplenum, pins in data:
-
-            # Ignore identical samples.
-            if self.prev_pins == pins:
-                continue
-            self.prev_pins = pins
-
-            # Have DATA processed at appropriate clock edges.
-            clock_pin, data_pin = pins[0], pins[1]
-            self.find_clk_edge(samplenum, clock_pin, data_pin)
+    def decode(self):
+        while True:
+            self.handle_clk_edge(*self.wait({0: 'e'}))