avr_isp: Fix a bug resulting in incorrect start samples.

[libsigrokdecode.git] / decoders / avr_isp / pd.py

diff --git a/decoders/avr_isp/pd.py b/decoders/avr_isp/pd.py
index 4b496e0249fc64e061944992e61cbe2df84c101a..05a46ec541295bfaaa2c88a90f05c1582a61a87b 100644 (file)
--- a/decoders/avr_isp/pd.py
+++ b/decoders/avr_isp/pd.py
@@ -1,5 +1,5 @@
 ##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
 ##
 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# AVR ISP protocol decoder
-
 import sigrokdecode as srd
 from .parts import *
 
@@ -29,7 +27,7 @@ class Decoder(srd.Decoder):
     api_version = 1
     id = 'avr_isp'
     name = 'AVR ISP'
-    longname = 'AVR in-system programming'
+    longname = 'AVR In-System Programming'
     desc = 'Protocol for in-system programming Atmel AVR MCUs.'
     license = 'gplv2+'
     inputs = ['spi', 'logic']
@@ -40,8 +38,8 @@ class Decoder(srd.Decoder):
     ]
     options = {}
     annotations = [
-        ['Text', 'Human-readable text'],
-        ['Warnings', 'Human-readable warnings'],
+        ['text', 'Human-readable text'],
+        ['warnings', 'Human-readable warnings'],
     ]
 
     def __init__(self, **kwargs):
@@ -50,12 +48,9 @@ class Decoder(srd.Decoder):
         self.cmd_ss, self.cmd_es = 0, 0
         self.xx, self.yy, self.zz, self.mm = 0, 0, 0, 0
 
-    def start(self, metadata):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'avr_isp')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'avr_isp')
-
-    def report(self):
-        pass
+    def start(self):
+        # self.out_python = self.register(srd.OUTPUT_PYTHON)
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putx(self, data):
         self.put(self.cmd_ss, self.cmd_es, self.out_ann, data)
@@ -116,9 +111,18 @@ class Decoder(srd.Decoder):
         self.xx, self.yy, self.zz, self.mm = 0, 0, 0, 0
 
     def handle_cmd_chip_erase(self, cmd, ret):
-        # TODO
+        # Chip erase (erases both flash an EEPROM).
+        # Upon successful chip erase, the lock bits will also be erased.
+        # The only way to end a Chip Erase cycle is to release RESET#.
         self.putx([0, ['Chip erase']])
 
+        # TODO: Check/handle RESET#.
+
+        # Sanity check on reply.
+        bit = (ret[2] & (1 << 7)) >> 7
+        if ret[1] != 0xac or bit != 1 or ret[3] != cmd[2]:
+            self.putx([1, ['Warning: Unexpected bytes in reply!']])
+
     def handle_cmd_read_fuse_bits(self, cmd, ret):
         # Read fuse bits.
         self.putx([0, ['Read fuse bits: 0x%02x' % ret[3]]])
@@ -173,13 +177,13 @@ class Decoder(srd.Decoder):
 
         self.ss, self.es = ss, es
 
+        if len(self.mosi_bytes) == 0:
+            self.cmd_ss = ss
+
         # Append new bytes.
         self.mosi_bytes.append(mosi)
         self.miso_bytes.append(miso)
 
-        if len(self.mosi_bytes) == 0:
-            self.cmd_ss = ss
-
         # All commands consist of 4 bytes.
         if len(self.mosi_bytes) < 4:
             return