desc = 'Audio and modem control for PC systems.'
license = 'gplv2+'
inputs = ['logic']
- outputs = ['ac97']
- tags = ['Logic', 'Audio']
+ outputs = []
+ tags = ['Audio', 'PC']
channels = (
{'id': 'sync', 'name': 'SYNC', 'desc': 'Frame synchronization'},
{'id': 'clk', 'name': 'BIT_CLK', 'desc': 'Data bits clock'},
{'id': 'rst', 'name': 'RESET#', 'desc': 'Reset line'},
)
annotations = (
- ('bit-out', 'Output bits'),
- ('bit-in', 'Input bits'),
+ ('bit-out', 'Output bit'),
+ ('bit-in', 'Input bit'),
('slot-out-raw', 'Output raw value'),
('slot-out-tag', 'Output TAG'),
('slot-out-cmd-addr', 'Output command address'),
self.put(ss, es, self.out_binary, [cls, data])
def __init__(self):
- self.out_binary = None
- self.out_ann = None
self.reset()
def reset(self):
}
def start(self):
- if not self.out_binary:
- self.out_binary = self.register(srd.OUTPUT_BINARY)
- if not self.out_ann:
- self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE: