X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fac97%2Fpd.py;h=adec12bcc081349722851f940476ce210affcff9;hp=8cb47a8c8d59dac08e2a770f4f359fe913b6d9a1;hb=e144452bcdd5f2abbe6b6f3da41ad64f67e39def;hpb=4c180223a8ae12feb7bc3601e07e848fb9cdb493

diff --git a/decoders/ac97/pd.py b/decoders/ac97/pd.py
index 8cb47a8..adec12b 100644
--- a/decoders/ac97/pd.py
+++ b/decoders/ac97/pd.py
@@ -59,8 +59,8 @@ class Decoder(srd.Decoder):
     desc = 'Audio and modem control for PC systems.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['ac97']
-    tags = ['Logic', 'Audio']
+    outputs = []
+    tags = ['Audio', 'PC']
     channels = (
         {'id': 'sync', 'name': 'SYNC', 'desc': 'Frame synchronization'},
         {'id': 'clk', 'name': 'BIT_CLK', 'desc': 'Data bits clock'},
@@ -71,8 +71,8 @@ class Decoder(srd.Decoder):
         {'id': 'rst', 'name': 'RESET#', 'desc': 'Reset line'},
     )
     annotations = (
-        ('bit-out', 'Output bits'),
-        ('bit-in', 'Input bits'),
+        ('bit-out', 'Output bit'),
+        ('bit-in', 'Input bit'),
         ('slot-out-raw', 'Output raw value'),
         ('slot-out-tag', 'Output TAG'),
         ('slot-out-cmd-addr', 'Output command address'),
@@ -153,8 +153,6 @@ class Decoder(srd.Decoder):
         self.put(ss, es, self.out_binary, [cls, data])
 
     def __init__(self):
-        self.out_binary = None
-        self.out_ann = None
         self.reset()
 
     def reset(self):
@@ -168,10 +166,8 @@ class Decoder(srd.Decoder):
         }
 
     def start(self):
-        if not self.out_binary:
-            self.out_binary = self.register(srd.OUTPUT_BINARY)
-        if not self.out_ann:
-            self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_binary = self.register(srd.OUTPUT_BINARY)
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE: