2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
39 - 'J', 'K', 'SE0', or 'SE1'
43 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
46 # Low-/full-speed symbols.
47 # Note: Low-speed J and K are inverted compared to the full-speed J and K!
50 # (<dp>, <dm>): <symbol/state>
57 # (<dp>, <dm>): <symbol/state>
66 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
67 'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
73 'SE0': [2, ['SE0', '0']],
74 'SE1': [3, ['SE1', '1']],
77 class SamplerateError(Exception):
80 class Decoder(srd.Decoder):
83 name = 'USB signalling'
84 longname = 'Universal Serial Bus (LS/FS) signalling'
85 desc = 'USB (low-speed and full-speed) signalling protocol.'
88 outputs = ['usb_signalling']
90 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
91 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
94 {'id': 'signalling', 'desc': 'Signalling',
95 'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
98 ('sym-j', 'J symbol'),
99 ('sym-k', 'K symbol'),
100 ('sym-se0', 'SE0 symbol'),
101 ('sym-se1', 'SE1 symbol'),
102 ('sop', 'Start of packet (SOP)'),
103 ('eop', 'End of packet (EOP)'),
105 ('stuffbit', 'Stuff bit'),
109 ('bits', 'Bits', (4, 5, 6, 7, 8)),
110 ('symbols', 'Symbols', (0, 1, 2, 3)),
114 self.samplerate = None
115 self.oldsym = 'J' # The "idle" state is J.
120 self.samplepos = None
121 self.samplenum_target = None
122 self.samplenum_edge = None
125 self.consecutive_ones = 0
129 self.out_python = self.register(srd.OUTPUT_PYTHON)
130 self.out_ann = self.register(srd.OUTPUT_ANN)
132 def metadata(self, key, value):
133 if key == srd.SRD_CONF_SAMPLERATE:
134 self.samplerate = value
135 self.bitrate = bitrates[self.options['signalling']]
136 self.bitwidth = float(self.samplerate) / float(self.bitrate)
137 self.halfbit = int(self.bitwidth / 2)
139 def putpx(self, data):
140 self.put(self.samplenum, self.samplenum, self.out_python, data)
142 def putx(self, data):
143 self.put(self.samplenum, self.samplenum, self.out_ann, data)
145 def putpm(self, data):
146 s, h = self.samplenum, self.halfbit
147 self.put(self.ss_block - h, s + h, self.out_python, data)
149 def putm(self, data):
150 s, h = self.samplenum, self.halfbit
151 self.put(self.ss_block - h, s + h, self.out_ann, data)
153 def putpb(self, data):
154 s, h = self.samplenum, self.halfbit
155 self.put(self.samplenum_edge, s + h, self.out_python, data)
157 def putb(self, data):
158 s, h = self.samplenum, self.halfbit
159 self.put(self.samplenum_edge, s + h, self.out_ann, data)
161 def set_new_target_samplenum(self):
162 self.samplepos += self.bitwidth;
163 self.samplenum_target = int(self.samplepos)
164 self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
166 def wait_for_sop(self, sym):
167 # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
171 self.consecutive_ones = 0
172 self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
173 self.set_new_target_samplenum()
174 self.putpx(['SOP', None])
175 self.putx([4, ['SOP', 'S']])
176 self.state = 'GET BIT'
178 def handle_bit(self, b):
179 if self.consecutive_ones == 6:
182 self.putpb(['STUFF BIT', None])
183 self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']])
184 self.consecutive_ones = 0
186 self.putpb(['ERR', None])
187 self.putb([8, ['Bit stuff error', 'BS ERR', 'B']])
190 # Normal bit (not a stuff bit).
191 self.putpb(['BIT', b])
192 self.putb([6, ['%s' % b]])
194 self.consecutive_ones += 1
196 self.consecutive_ones = 0
198 def get_eop(self, sym):
199 # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
200 self.putpb(['SYM', sym])
201 self.putb(sym_annotation[sym])
202 self.set_new_target_samplenum()
208 self.putpm(['EOP', None])
209 self.putm([5, ['EOP', 'E']])
211 self.bitwidth = float(self.samplerate) / float(self.bitrate)
213 def get_bit(self, sym):
215 # Start of an EOP. Change state, save edge
216 self.state = 'GET EOP'
217 self.ss_block = self.samplenum
219 b = '0' if self.oldsym != sym else '1'
221 self.putpb(['SYM', sym])
222 self.putb(sym_annotation[sym])
223 if self.oldsym != sym:
224 edgesym = symbols[self.options['signalling']][tuple(self.edgepins)]
225 if edgesym not in ('SE0', 'SE1'):
227 self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
228 self.samplepos = self.samplepos - (0.01 * self.bitwidth)
230 self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
231 self.samplepos = self.samplepos + (0.01 * self.bitwidth)
232 self.set_new_target_samplenum()
235 def decode(self, ss, es, data):
236 if not self.samplerate:
237 raise SamplerateError('Cannot decode without samplerate.')
238 for (self.samplenum, pins) in data:
240 if self.state == 'IDLE':
241 # Ignore identical samples early on (for performance reasons).
242 if self.oldpins == pins:
245 sym = symbols[self.options['signalling']][tuple(pins)]
246 self.wait_for_sop(sym)
248 elif self.state in ('GET BIT', 'GET EOP'):
249 # Wait until we're in the middle of the desired bit.
250 if self.samplenum == self.samplenum_edge:
252 if self.samplenum < self.samplenum_target:
254 sym = symbols[self.options['signalling']][tuple(pins)]
255 if self.state == 'GET BIT':
257 elif self.state == 'GET EOP':