2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
38 - 'J', 'K', 'SE0', or 'SE1'
42 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
45 # Low-/full-speed symbols.
46 # Note: Low-speed J and K are inverted compared to the full-speed J and K!
49 # (<dp>, <dm>): <symbol/state>
56 # (<dp>, <dm>): <symbol/state>
65 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
66 'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
69 class Decoder(srd.Decoder):
72 name = 'USB signalling'
73 longname = 'Universal Serial Bus (LS/FS) signalling'
74 desc = 'USB (low-speed and full-speed) signalling protocol.'
77 outputs = ['usb_signalling']
79 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
80 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
84 'signalling': ['Signalling', 'full-speed'],
88 ['sop', 'Start of packet (SOP)'],
89 ['eop', 'End of packet (EOP)'],
91 ['stuffbit', 'Stuff bit'],
94 ('bits', 'Bits', (1, 2, 3, 4)),
95 ('symbols', 'Symbols', (0,)),
99 self.samplerate = None
100 self.oldsym = 'J' # The "idle" state is J.
108 self.samplenum_target = None
110 self.consecutive_ones = 0
114 self.out_python = self.register(srd.OUTPUT_PYTHON)
115 self.out_ann = self.register(srd.OUTPUT_ANN)
117 def metadata(self, key, value):
118 if key == srd.SRD_CONF_SAMPLERATE:
119 self.samplerate = value
120 self.bitrate = bitrates[self.options['signalling']]
121 self.bitwidth = float(self.samplerate) / float(self.bitrate)
122 self.halfbit = int(self.bitwidth / 2)
124 def putpx(self, data):
125 self.put(self.samplenum, self.samplenum, self.out_python, data)
127 def putx(self, data):
128 self.put(self.samplenum, self.samplenum, self.out_ann, data)
130 def putpm(self, data):
131 s, h = self.samplenum, self.halfbit
132 self.put(self.ss_block - h, s + h, self.out_python, data)
134 def putm(self, data):
135 s, h = self.samplenum, self.halfbit
136 self.put(self.ss_block - h, s + h, self.out_ann, data)
138 def putpb(self, data):
139 s, h = self.samplenum, self.halfbit
140 self.put(s - h, s + h, self.out_python, data)
142 def putb(self, data):
143 s, h = self.samplenum, self.halfbit
144 self.put(s - h, s + h, self.out_ann, data)
146 def set_new_target_samplenum(self):
147 bitpos = self.ss_sop + (self.bitwidth / 2)
148 bitpos += self.bitnum * self.bitwidth
149 self.samplenum_target = int(bitpos)
151 def wait_for_sop(self, sym):
152 # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
156 self.ss_sop = self.samplenum
157 self.set_new_target_samplenum()
158 self.putpx(['SOP', None])
159 self.putx([1, ['SOP']])
160 self.state = 'GET BIT'
162 def handle_bit(self, sym, b):
163 if self.consecutive_ones == 6 and b == '0':
165 self.putpb(['STUFF BIT', None])
166 self.putb([4, ['SB: %s' % b]])
167 self.putb([0, ['%s' % sym]])
168 self.consecutive_ones = 0
170 # Normal bit (not a stuff bit).
171 self.putpb(['BIT', b])
172 self.putb([3, ['%s' % b]])
173 self.putb([0, ['%s' % sym]])
175 self.consecutive_ones += 1
177 self.consecutive_ones = 0
179 def get_eop(self, sym):
180 # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
181 self.syms.append(sym)
182 self.putpb(['SYM', sym])
183 self.putb([0, ['%s' % sym]])
185 self.set_new_target_samplenum()
187 if self.syms[-2:] == ['SE0', 'J']:
189 self.putpm(['EOP', None])
190 self.putm([2, ['EOP']])
191 self.bitnum, self.syms, self.state = 0, [], 'IDLE'
192 self.consecutive_ones = 0
194 def get_bit(self, sym):
196 # Start of an EOP. Change state, run get_eop() for this bit.
197 self.state = 'GET EOP'
198 self.ss_block = self.samplenum
201 self.syms.append(sym)
202 self.putpb(['SYM', sym])
203 b = '0' if self.oldsym != sym else '1'
204 self.handle_bit(sym, b)
206 self.set_new_target_samplenum()
209 def decode(self, ss, es, data):
210 if self.samplerate is None:
211 raise Exception("Cannot decode without samplerate.")
212 for (self.samplenum, pins) in data:
214 if self.state == 'IDLE':
215 # Ignore identical samples early on (for performance reasons).
216 if self.oldpins == pins:
219 sym = symbols[self.options['signalling']][tuple(pins)]
220 self.wait_for_sop(sym)
221 elif self.state in ('GET BIT', 'GET EOP'):
222 # Wait until we're in the middle of the desired bit.
223 if self.samplenum < self.samplenum_target:
225 sym = symbols[self.options['signalling']][tuple(pins)]
226 if self.state == 'GET BIT':
228 elif self.state == 'GET EOP':
231 raise Exception('Invalid state: %s' % self.state)