2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
5 ## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com>
6 ## Copyright (C) 2014 alberink <alberink@stampfini.org>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
22 import sigrokdecode as srd
24 NUM_OUTPUT_CHANNELS = 8
26 def logic_channels(num_channels):
28 for i in range(num_channels):
29 l.append(tuple(['p%d' % i, 'P-port input/output %d' % i]))
32 class Decoder(srd.Decoder):
36 longname = 'Texas Instruments TCA6408A'
37 desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.'
41 tags = ['Embedded/industrial', 'IC']
43 ('register', 'Register type'),
44 ('value', 'Register value'),
45 ('warning', 'Warning'),
47 logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS)
49 ('regs', 'Registers', (0, 1)),
50 ('warnings', 'Warnings', (2,)),
62 for i in range(NUM_OUTPUT_CHANNELS):
63 self.logic_data.append(bytes([1]))
66 self.out_ann = self.register(srd.OUTPUT_ANN)
67 self.out_logic = self.register(srd.OUTPUT_LOGIC)
70 self.put(self.ss, self.es, self.out_ann, data)
72 def put_logic_states(self):
73 if (self.es > self.logic_es):
74 for i in range(NUM_OUTPUT_CHANNELS):
75 self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]])
76 self.logic_es = self.es
78 def handle_reg_0x00(self, b):
79 self.putx([1, ['State of inputs: %02X' % b]])
82 def handle_reg_0x01(self, b):
83 self.putx([1, ['Outputs set: %02X' % b]])
84 for i in range(NUM_OUTPUT_CHANNELS):
85 bit = (b & (1 << i)) != 0
86 self.logic_data[i] = bytes([bit])
88 def handle_reg_0x02(self, b):
89 self.putx([1, ['Polarity inverted: %02X' % b]])
91 def handle_reg_0x03(self, b):
92 self.putx([1, ['Configuration: %02X' % b]])
94 def handle_write_reg(self, b):
96 self.putx([0, ['Input port', 'In', 'I']])
98 self.putx([0, ['Output port', 'Out', 'O']])
100 self.putx([0, ['Polarity inversion register', 'Pol', 'P']])
102 self.putx([0, ['Configuration register', 'Conf', 'C']])
104 def check_correct_chip(self, addr):
105 if addr not in (0x20, 0x21):
106 self.putx([2, ['Warning: I²C slave 0x%02X not a TCA6408A '
107 'compatible chip.' % addr]])
110 def decode(self, ss, es, data):
113 # Store the start/end samples of this I²C packet.
114 self.ss, self.es = ss, es
116 self.put_logic_states()
119 if self.state == 'IDLE':
120 # Wait for an I²C START condition.
123 self.state = 'GET SLAVE ADDR'
124 elif self.state == 'GET SLAVE ADDR':
126 self.state = 'GET REG ADDR'
127 elif self.state == 'GET REG ADDR':
128 # Wait for a data write (master selects the slave register).
129 if cmd in ('ADDRESS READ', 'ADDRESS WRITE'):
130 self.check_correct_chip(databyte)
131 if cmd != 'DATA WRITE':
134 self.handle_write_reg(self.reg)
135 self.state = 'WRITE IO REGS'
136 elif self.state == 'WRITE IO REGS':
137 # If we see a Repeated Start here, the master wants to read.
138 if cmd == 'START REPEAT':
139 self.state = 'READ IO REGS'
141 # Otherwise: Get data bytes until a STOP condition occurs.
142 if cmd == 'DATA WRITE':
143 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
148 elif self.state == 'READ IO REGS':
149 # Wait for an address read operation.
150 if cmd == 'ADDRESS READ':
151 self.state = 'READ IO REGS2'
154 elif self.state == 'READ IO REGS2':
155 if cmd == 'DATA READ':
156 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)