2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2015 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
24 def cmd_annotation_classes():
25 return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()])
27 def decode_dual_bytes(sio0, sio1):
28 # Given a byte in SIO0 (MOSI) of even bits and a byte in
29 # SIO1 (MISO) of odd bits, return a tuple of two bytes.
30 def combine_byte(even, odd):
34 result |= 1 << (bit*2)
36 result |= 1 << ((bit*2) + 1)
38 return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1))
40 def decode_status_reg(data):
41 # TODO: Additional per-bit(s) self.put() calls with correct start/end.
43 # Bits[0:0]: WIP (write in progress)
44 s = 'W' if (data & (1 << 0)) else 'No w'
45 ret = '%srite operation in progress.\n' % s
47 # Bits[1:1]: WEL (write enable latch)
48 s = '' if (data & (1 << 1)) else 'not '
49 ret += 'Internal write enable latch is %sset.\n' % s
51 # Bits[5:2]: Block protect bits
52 # TODO: More detailed decoding (chip-dependent).
53 ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
55 # Bits[6:6]: Continuously program mode (CP mode)
56 s = '' if (data & (1 << 6)) else 'not '
57 ret += 'Device is %sin continuously program mode (CP mode).\n' % s
59 # Bits[7:7]: SRWD (status register write disable)
60 s = 'not ' if (data & (1 << 7)) else ''
61 ret += 'Status register writes are %sallowed.\n' % s
65 class Decoder(srd.Decoder):
69 longname = 'SPI flash chips'
70 desc = 'xx25 series SPI (NOR) flash chip protocol.'
73 outputs = ['spiflash']
74 annotations = cmd_annotation_classes() + (
77 ('warnings', 'Warnings'),
80 ('bits', 'Bits', (24, 25)),
81 ('commands', 'Commands', tuple(range(23 + 1))),
82 ('warnings', 'Warnings', (26,)),
85 {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0],
86 'values': tuple(chips.keys())},
87 {'id': 'format', 'desc': 'Data format', 'default': 'hex',
88 'values': ('hex', 'ascii')},
93 self.on_end_transaction = None
94 self.end_current_transaction()
96 # Build dict mapping command keys to handler functions. Each
97 # command in 'cmds' (defined in lists.py) has a matching
98 # handler self.handle_<shortname>.
100 s = 'handle_%s' % cmds[cmd][0].lower().replace('/', '_')
101 return getattr(self, s)
102 self.cmd_handlers = dict((cmd, get_handler(cmd)) for cmd in cmds.keys())
104 def end_current_transaction(self):
105 if self.on_end_transaction is not None: # Callback for CS# transition.
106 self.on_end_transaction()
107 self.on_end_transaction = None
114 self.out_ann = self.register(srd.OUTPUT_ANN)
115 self.chip = chips[self.options['chip']]
116 self.vendor = self.options['chip'].split('_')[0]
118 def putx(self, data):
119 # Simplification, most annotations span exactly one SPI byte/packet.
120 self.put(self.ss, self.es, self.out_ann, data)
122 def putb(self, data):
123 self.put(self.ss_block, self.es_block, self.out_ann, data)
125 def vendor_device(self):
126 dev = device_name[self.vendor].get(self.device_id, 'Unknown')
127 return '%s %s' % (self.chip['vendor'], dev)
129 def handle_wren(self, mosi, miso):
130 self.putx([0, ['Command: %s' % cmds[self.state][1]]])
133 def handle_wrdi(self, mosi, miso):
136 # TODO: Check/display device ID / name
137 def handle_rdid(self, mosi, miso):
138 if self.cmdstate == 1:
139 # Byte 1: Master sends command ID.
140 self.ss_block = self.ss
141 self.putx([2, ['Command: %s' % cmds[self.state][1]]])
142 elif self.cmdstate == 2:
143 # Byte 2: Slave sends the JEDEC manufacturer ID.
144 self.putx([2, ['Manufacturer ID: 0x%02x' % miso]])
145 elif self.cmdstate == 3:
146 # Byte 3: Slave sends the memory type (0x20 for this chip).
147 self.putx([2, ['Memory type: 0x%02x' % miso]])
148 elif self.cmdstate == 4:
149 # Byte 4: Slave sends the device ID.
150 self.device_id = miso
151 self.putx([2, ['Device ID: 0x%02x' % miso]])
153 if self.cmdstate == 4:
154 # TODO: Same device ID? Check!
155 d = 'Device: %s' % self.vendor_device()
156 self.put(self.ss_block, self.es, self.out_ann, [0, [d]])
161 def handle_rdsr(self, mosi, miso):
162 # Read status register: Master asserts CS#, sends RDSR command,
163 # reads status register byte. If CS# is kept asserted, the status
164 # register can be read continuously / multiple times in a row.
165 # When done, the master de-asserts CS# again.
166 if self.cmdstate == 1:
167 # Byte 1: Master sends command ID.
168 self.putx([3, ['Command: %s' % cmds[self.state][1]]])
169 elif self.cmdstate >= 2:
170 # Bytes 2-x: Slave sends status register as long as master clocks.
171 self.putx([24, ['Status register: 0x%02x' % miso]])
172 self.putx([25, [decode_status_reg(miso)]])
176 def handle_wrsr(self, mosi, miso):
177 # Write status register: Master asserts CS#, sends WRSR command,
178 # writes 1 or 2 status register byte(s).
179 # When done, the master de-asserts CS# again. If this doesn't happen
180 # the WRSR command will not be executed.
181 if self.cmdstate == 1:
182 # Byte 1: Master sends command ID.
183 self.putx([3, ['Command: %s' % cmds[self.state][1]]])
184 elif self.cmdstate in (2, 3):
185 # Bytes 2 and/or 3: Master sends status register byte(s).
186 self.putx([24, ['Status register: 0x%02x' % miso]])
187 self.putx([25, [decode_status_reg(miso)]])
188 # TODO: Handle status register 2 correctly.
192 def handle_read(self, mosi, miso):
193 # Read data bytes: Master asserts CS#, sends READ command, sends
194 # 3-byte address, reads >= 1 data bytes, de-asserts CS#.
195 if self.cmdstate == 1:
196 # Byte 1: Master sends command ID.
197 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
198 elif self.cmdstate in (2, 3, 4):
199 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
200 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
201 # self.putx([0, ['Read address, byte %d: 0x%02x' % \
202 # (4 - self.cmdstate, mosi)]])
203 if self.cmdstate == 4:
204 self.putx([24, ['Read address: 0x%06x' % self.addr]])
206 elif self.cmdstate >= 5:
207 # Bytes 5-x: Master reads data bytes (until CS# de-asserted).
208 if self.cmdstate == 5:
209 self.ss_block = self.ss
210 self.on_end_transaction = lambda: self.output_data_block('Read')
211 self.data.append(miso)
215 def handle_fast_read(self, mosi, miso):
216 # Fast read: Master asserts CS#, sends FAST READ command, sends
217 # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#.
218 if self.cmdstate == 1:
219 # Byte 1: Master sends command ID.
220 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
221 elif self.cmdstate in (2, 3, 4):
222 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
223 self.putx([24, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]])
224 if self.cmdstate == 2:
225 self.ss_block = self.ss
226 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
227 elif self.cmdstate == 5:
228 self.putx([24, ['Dummy byte: 0x%02x' % mosi]])
229 self.es_block = self.es
230 self.putb([5, ['Read address: 0x%06x' % self.addr]])
232 elif self.cmdstate >= 6:
233 # Bytes 6-x: Master reads data bytes (until CS# de-asserted).
234 if self.cmdstate == 6:
235 self.ss_block = self.ss
236 self.on_end_transaction = lambda: self.output_data_block('Read')
237 self.data.append(miso)
241 def handle_2read(self, mosi, miso):
242 # Fast read dual I/O: Same as fast read, but all data
243 # after the command is sent via two I/O pins.
244 # MOSI = SIO0 = even bits, MISO = SIO1 = odd bits.
245 # Recombine the bytes and pass them up to the handle_fast_read command.
246 if self.cmdstate == 1:
247 # Byte 1: Master sends command ID.
248 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
252 a, b = decode_dual_bytes(mosi, miso)
253 # Pass same byte in as both MISO & MOSI, parser state determines
254 # which one it cares about.
255 self.handle_fast_read(a, a)
256 self.handle_fast_read(b, b)
258 # TODO: Warn/abort if we don't see the necessary amount of bytes.
259 # TODO: Warn if WREN was not seen before.
260 def handle_se(self, mosi, miso):
261 if self.cmdstate == 1:
262 # Byte 1: Master sends command ID.
264 self.ss_block = self.ss
265 self.putx([8, ['Command: %s' % cmds[self.state][1]]])
266 elif self.cmdstate in (2, 3, 4):
267 # Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
268 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
269 # self.putx([0, ['Sector address, byte %d: 0x%02x' % \
270 # (4 - self.cmdstate, mosi)]])
272 if self.cmdstate == 4:
273 d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
274 self.put(self.ss_block, self.es, self.out_ann, [24, [d]])
275 # TODO: Max. size depends on chip, check that too if possible.
276 if self.addr % 4096 != 0:
277 # Sector addresses must be 4K-aligned (same for all 3 chips).
278 d = 'Warning: Invalid sector address!'
279 self.put(self.ss_block, self.es, self.out_ann, [101, [d]])
284 def handle_be(self, mosi, miso):
287 def handle_ce(self, mosi, miso):
290 def handle_ce2(self, mosi, miso):
293 def handle_pp(self, mosi, miso):
294 # Page program: Master asserts CS#, sends PP command, sends 3-byte
295 # page address, sends >= 1 data bytes, de-asserts CS#.
296 if self.cmdstate == 1:
297 # Byte 1: Master sends command ID.
298 self.putx([12, ['Command: %s' % cmds[self.state][1]]])
299 elif self.cmdstate in (2, 3, 4):
300 # Bytes 2/3/4: Master sends page address (24bits, MSB-first).
301 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
302 # self.putx([0, ['Page address, byte %d: 0x%02x' % \
303 # (4 - self.cmdstate, mosi)]])
304 if self.cmdstate == 4:
305 self.putx([24, ['Page address: 0x%06x' % self.addr]])
307 elif self.cmdstate >= 5:
308 # Bytes 5-x: Master sends data bytes (until CS# de-asserted).
309 if self.cmdstate == 5:
310 self.ss_block = self.ss
311 self.on_end_transaction = lambda: self.output_data_block('Page data')
312 self.data.append(mosi)
316 def handle_cp(self, mosi, miso):
319 def handle_dp(self, mosi, miso):
322 def handle_rdp_res(self, mosi, miso):
323 if self.cmdstate == 1:
324 # Byte 1: Master sends command ID.
325 self.ss_block = self.ss
326 self.putx([16, ['Command: %s' % cmds[self.state][1]]])
327 elif self.cmdstate in (2, 3, 4):
328 # Bytes 2/3/4: Master sends three dummy bytes.
329 self.putx([24, ['Dummy byte: %02x' % mosi]])
330 elif self.cmdstate == 5:
331 # Byte 5: Slave sends device ID.
332 self.device_id = miso
333 self.putx([24, ['Device: %s' % self.vendor_device()]])
338 def handle_rems(self, mosi, miso):
339 if self.cmdstate == 1:
340 # Byte 1: Master sends command ID.
341 self.ss_block = self.ss
342 self.putx([16, ['Command: %s' % cmds[self.state][1]]])
343 elif self.cmdstate in (2, 3):
344 # Bytes 2/3: Master sends two dummy bytes.
345 # TODO: Check dummy bytes? Check reply from device?
346 self.putx([24, ['Dummy byte: %s' % mosi]])
347 elif self.cmdstate == 4:
348 # Byte 4: Master sends 0x00 or 0x01.
349 # 0x00: Master wants manufacturer ID as first reply byte.
350 # 0x01: Master wants device ID as first reply byte.
351 self.manufacturer_id_first = True if (mosi == 0x00) else False
352 d = 'manufacturer' if (mosi == 0x00) else 'device'
353 self.putx([24, ['Master wants %s ID first' % d]])
354 elif self.cmdstate == 5:
355 # Byte 5: Slave sends manufacturer ID (or device ID).
357 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
358 self.putx([24, ['%s ID' % d]])
359 elif self.cmdstate == 6:
360 # Byte 6: Slave sends device ID (or manufacturer ID).
361 self.ids.append(miso)
362 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
363 self.putx([24, ['%s ID' % d]])
365 if self.cmdstate == 6:
366 id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
368 self.putx([24, ['Device: %s' % self.vendor_device()]])
373 def handle_rems2(self, mosi, miso):
376 def handle_enso(self, mosi, miso):
379 def handle_exso(self, mosi, miso):
382 def handle_rdscur(self, mosi, miso):
385 def handle_wrscur(self, mosi, miso):
388 def handle_esry(self, mosi, miso):
391 def handle_dsry(self, mosi, miso):
394 def output_data_block(self, label):
395 # Print accumulated block of data
396 # (called on CS# de-assert via self.on_end_transaction callback).
397 self.es_block = self.es # Ends on the CS# de-assert sample.
398 if self.options['format'] == 'hex':
399 s = ' '.join([('%02x' % b) for b in self.data])
401 s = ''.join(map(chr, self.data))
402 self.putb([25, ['%s %d bytes: %s' % (label, len(self.data), s)]])
404 def decode(self, ss, es, data):
405 ptype, mosi, miso = data
407 self.ss, self.es = ss, es
409 if ptype == 'CS-CHANGE':
410 self.end_current_transaction()
415 # If we encountered a known chip command, enter the resp. state.
416 if self.state is None:
422 self.cmd_handlers[self.state](mosi, miso)
424 self.putx([24, ['Unknown command: 0x%02x' % mosi]])