2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2015 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
24 def cmd_annotation_classes():
25 return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()])
27 def decode_dual_bytes(sio0, sio1):
28 # Given a byte in SIO0 (MOSI) of even bits and a byte in
29 # SIO1 (MISO) of odd bits, return a tuple of two bytes.
30 def combine_byte(even, odd):
34 result |= 1 << (bit*2)
36 result |= 1 << ((bit*2) + 1)
38 return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1))
40 def decode_status_reg(data):
41 # TODO: Additional per-bit(s) self.put() calls with correct start/end.
43 # Bits[0:0]: WIP (write in progress)
44 s = 'W' if (data & (1 << 0)) else 'No w'
45 ret = '%srite operation in progress.\n' % s
47 # Bits[1:1]: WEL (write enable latch)
48 s = '' if (data & (1 << 1)) else 'not '
49 ret += 'Internal write enable latch is %sset.\n' % s
51 # Bits[5:2]: Block protect bits
52 # TODO: More detailed decoding (chip-dependent).
53 ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
55 # Bits[6:6]: Continuously program mode (CP mode)
56 s = '' if (data & (1 << 6)) else 'not '
57 ret += 'Device is %sin continuously program mode (CP mode).\n' % s
59 # Bits[7:7]: SRWD (status register write disable)
60 s = 'not ' if (data & (1 << 7)) else ''
61 ret += 'Status register writes are %sallowed.\n' % s
65 class Decoder(srd.Decoder):
69 longname = 'SPI flash chips'
70 desc = 'xx25 series SPI (NOR) flash chip protocol.'
73 outputs = ['spiflash']
74 annotations = cmd_annotation_classes() + (
77 ('warnings', 'Warnings'),
80 ('bits', 'Bits', (24, 25)),
81 ('commands', 'Commands', tuple(range(23 + 1))),
82 ('warnings', 'Warnings', (26,)),
85 {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0],
86 'values': tuple(chips.keys())},
90 self.on_end_transaction = None
91 self.end_current_transaction()
93 # Build dict mapping command keys to handler functions. Each
94 # command in 'cmds' (defined in lists.py) has a matching
95 # handler self.handle_<shortname>.
97 s = 'handle_%s' % cmds[cmd][0].lower().replace('/', '_')
98 return getattr(self, s)
99 self.cmd_handlers = dict((cmd, get_handler(cmd)) for cmd in cmds.keys())
101 def end_current_transaction(self):
102 if self.on_end_transaction is not None: # Callback for CS# transition.
103 self.on_end_transaction()
104 self.on_end_transaction = None
111 self.out_ann = self.register(srd.OUTPUT_ANN)
112 self.chip = chips[self.options['chip']]
114 def putx(self, data):
115 # Simplification, most annotations span exactly one SPI byte/packet.
116 self.put(self.ss, self.es, self.out_ann, data)
118 def putb(self, data):
119 self.put(self.ss_block, self.es_block, self.out_ann, data)
121 def handle_wren(self, mosi, miso):
122 self.putx([0, ['Command: %s' % cmds[self.state][1]]])
125 def handle_wrdi(self, mosi, miso):
128 # TODO: Check/display device ID / name
129 def handle_rdid(self, mosi, miso):
130 if self.cmdstate == 1:
131 # Byte 1: Master sends command ID.
132 self.ss_block = self.ss
133 self.putx([2, ['Command: %s' % cmds[self.state][1]]])
134 elif self.cmdstate == 2:
135 # Byte 2: Slave sends the JEDEC manufacturer ID.
136 self.putx([2, ['Manufacturer ID: 0x%02x' % miso]])
137 elif self.cmdstate == 3:
138 # Byte 3: Slave sends the memory type (0x20 for this chip).
139 self.putx([2, ['Memory type: 0x%02x' % miso]])
140 elif self.cmdstate == 4:
141 # Byte 4: Slave sends the device ID.
142 self.device_id = miso
143 self.putx([2, ['Device ID: 0x%02x' % miso]])
145 if self.cmdstate == 4:
146 # TODO: Check self.device_id is valid & exists in device_names.
147 # TODO: Same device ID? Check!
148 d = 'Device: Macronix %s' % device_name[self.device_id]
149 self.put(self.ss_block, self.es, self.out_ann, [0, [d]])
154 def handle_rdsr(self, mosi, miso):
155 # Read status register: Master asserts CS#, sends RDSR command,
156 # reads status register byte. If CS# is kept asserted, the status
157 # register can be read continuously / multiple times in a row.
158 # When done, the master de-asserts CS# again.
159 if self.cmdstate == 1:
160 # Byte 1: Master sends command ID.
161 self.putx([3, ['Command: %s' % cmds[self.state][1]]])
162 elif self.cmdstate >= 2:
163 # Bytes 2-x: Slave sends status register as long as master clocks.
164 self.putx([24, ['Status register: 0x%02x' % miso]])
165 self.putx([25, [decode_status_reg(miso)]])
169 def handle_wrsr(self, mosi, miso):
172 def handle_read(self, mosi, miso):
173 # Read data bytes: Master asserts CS#, sends READ command, sends
174 # 3-byte address, reads >= 1 data bytes, de-asserts CS#.
175 if self.cmdstate == 1:
176 # Byte 1: Master sends command ID.
177 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
178 elif self.cmdstate in (2, 3, 4):
179 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
180 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
181 # self.putx([0, ['Read address, byte %d: 0x%02x' % \
182 # (4 - self.cmdstate, mosi)]])
183 if self.cmdstate == 4:
184 self.putx([24, ['Read address: 0x%06x' % self.addr]])
186 elif self.cmdstate >= 5:
187 # Bytes 5-x: Master reads data bytes (until CS# de-asserted).
188 if self.cmdstate == 5:
189 self.ss_block = self.ss
190 self.on_end_transaction = lambda: self.output_data_block('Read')
191 self.data.append(miso)
195 def handle_fast_read(self, mosi, miso):
196 # Fast read: Master asserts CS#, sends FAST READ command, sends
197 # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#.
198 if self.cmdstate == 1:
199 # Byte 1: Master sends command ID.
200 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
201 elif self.cmdstate in (2, 3, 4):
202 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
203 self.putx([24, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]])
204 if self.cmdstate == 2:
205 self.ss_block = self.ss
206 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
207 elif self.cmdstate == 5:
208 self.putx([24, ['Dummy byte: 0x%02x' % mosi]])
209 self.es_block = self.es
210 self.putb([5, ['Read address: 0x%06x' % self.addr]])
212 elif self.cmdstate >= 6:
213 # Bytes 6-x: Master reads data bytes (until CS# de-asserted).
214 if self.cmdstate == 6:
215 self.ss_block = self.ss
216 self.on_end_transaction = lambda: self.output_data_block('Read')
217 self.data.append(miso)
221 def handle_2read(self, mosi, miso):
222 # Fast read dual I/O: Same as fast read, but all data
223 # after the command is sent via two I/O pins.
224 # MOSI = SIO0 = even bits, MISO = SIO1 = odd bits.
225 # Recombine the bytes and pass them up to the handle_fast_read command.
226 if self.cmdstate == 1:
227 # Byte 1: Master sends command ID.
228 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
232 a, b = decode_dual_bytes(mosi, miso)
233 # Pass same byte in as both MISO & MOSI, parser state determines
234 # which one it cares about.
235 self.handle_fast_read(a, a)
236 self.handle_fast_read(b, b)
238 # TODO: Warn/abort if we don't see the necessary amount of bytes.
239 # TODO: Warn if WREN was not seen before.
240 def handle_se(self, mosi, miso):
241 if self.cmdstate == 1:
242 # Byte 1: Master sends command ID.
244 self.ss_block = self.ss
245 self.putx([8, ['Command: %s' % cmds[self.state][1]]])
246 elif self.cmdstate in (2, 3, 4):
247 # Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
248 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
249 # self.putx([0, ['Sector address, byte %d: 0x%02x' % \
250 # (4 - self.cmdstate, mosi)]])
252 if self.cmdstate == 4:
253 d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
254 self.put(self.ss_block, self.es, self.out_ann, [24, [d]])
255 # TODO: Max. size depends on chip, check that too if possible.
256 if self.addr % 4096 != 0:
257 # Sector addresses must be 4K-aligned (same for all 3 chips).
258 d = 'Warning: Invalid sector address!'
259 self.put(self.ss_block, self.es, self.out_ann, [101, [d]])
264 def handle_be(self, mosi, miso):
267 def handle_ce(self, mosi, miso):
270 def handle_ce2(self, mosi, miso):
273 def handle_pp(self, mosi, miso):
274 # Page program: Master asserts CS#, sends PP command, sends 3-byte
275 # page address, sends >= 1 data bytes, de-asserts CS#.
276 if self.cmdstate == 1:
277 # Byte 1: Master sends command ID.
278 self.putx([12, ['Command: %s' % cmds[self.state][1]]])
279 elif self.cmdstate in (2, 3, 4):
280 # Bytes 2/3/4: Master sends page address (24bits, MSB-first).
281 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
282 # self.putx([0, ['Page address, byte %d: 0x%02x' % \
283 # (4 - self.cmdstate, mosi)]])
284 if self.cmdstate == 4:
285 self.putx([24, ['Page address: 0x%06x' % self.addr]])
287 elif self.cmdstate >= 5:
288 # Bytes 5-x: Master sends data bytes (until CS# de-asserted).
289 if self.cmdstate == 5:
290 self.ss_block = self.ss
291 self.on_end_transaction = lambda: self.output_data_block('Page data')
292 self.data.append(mosi)
296 def handle_cp(self, mosi, miso):
299 def handle_dp(self, mosi, miso):
302 def handle_rdp_res(self, mosi, miso):
305 def handle_rems(self, mosi, miso):
306 if self.cmdstate == 1:
307 # Byte 1: Master sends command ID.
308 self.ss_block = self.ss
309 self.putx([16, ['Command: %s' % cmds[self.state][1]]])
310 elif self.cmdstate in (2, 3):
311 # Bytes 2/3: Master sends two dummy bytes.
312 # TODO: Check dummy bytes? Check reply from device?
313 self.putx([24, ['Dummy byte: %s' % mosi]])
314 elif self.cmdstate == 4:
315 # Byte 4: Master sends 0x00 or 0x01.
316 # 0x00: Master wants manufacturer ID as first reply byte.
317 # 0x01: Master wants device ID as first reply byte.
318 self.manufacturer_id_first = True if (mosi == 0x00) else False
319 d = 'manufacturer' if (mosi == 0x00) else 'device'
320 self.putx([24, ['Master wants %s ID first' % d]])
321 elif self.cmdstate == 5:
322 # Byte 5: Slave sends manufacturer ID (or device ID).
324 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
325 self.putx([24, ['%s ID' % d]])
326 elif self.cmdstate == 6:
327 # Byte 6: Slave sends device ID (or manufacturer ID).
328 self.ids.append(miso)
329 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
330 self.putx([24, ['%s ID' % d]])
332 if self.cmdstate == 6:
333 id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
334 self.putx([24, ['Device: Macronix %s' % device_name[id]]])
339 def handle_rems2(self, mosi, miso):
342 def handle_enso(self, mosi, miso):
345 def handle_exso(self, mosi, miso):
348 def handle_rdscur(self, mosi, miso):
351 def handle_wrscur(self, mosi, miso):
354 def handle_esry(self, mosi, miso):
357 def handle_dsry(self, mosi, miso):
360 def output_data_block(self, label):
361 # Print accumulated block of data
362 # (called on CS# de-assert via self.on_end_transaction callback).
363 self.es_block = self.es # Ends on the CS# de-assert sample.
364 s = ' '.join([('%02x' % b) for b in self.data])
365 self.putb([25, ['%s %d bytes: %s' % (label, len(self.data), s)]])
367 def decode(self, ss, es, data):
368 ptype, mosi, miso = data
370 self.ss, self.es = ss, es
372 if ptype == 'CS-CHANGE':
373 self.end_current_transaction()
378 # If we encountered a known chip command, enter the resp. state.
379 if self.state is None:
385 self.cmd_handlers[self.state](mosi, miso)
387 self.putx([24, ['Unknown command: 0x%02x' % mosi]])