2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # SPI protocol decoder
24 import sigrokdecode as srd
26 # Key: (CPOL, CPHA). Value: SPI mode.
27 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
28 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
39 class Decoder(srd.Decoder):
43 longname = 'Serial Peripheral Interface'
45 longdesc = '...longdesc...'
50 {'id': 'miso', 'name': 'MISO',
51 'desc': 'SPI MISO line (Master in, slave out)'},
52 {'id': 'mosi', 'name': 'MOSI',
53 'desc': 'SPI MOSI line (Master out, slave in)'},
54 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
55 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
57 optional_probes = [] # TODO
59 'cs_polarity': ['CS# polarity', 'active-low'],
60 'cpol': ['Clock polarity', 0],
61 'cpha': ['Clock phase', 0],
62 'bitorder': ['Bit order within the SPI data', 'msb-first'],
63 'wordsize': ['Word size of SPI data', 8], # 1-64?
66 ['Hex', 'SPI data bytes in hex format'],
74 self.bytesreceived = 0
76 self.cs_was_deasserted_during_data_word = 0
78 def start(self, metadata):
79 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
80 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
83 return 'SPI: %d bytes received' % self.bytesreceived
85 def decode(self, ss, es, data):
86 # TODO: Either MISO or MOSI could be optional. CS# is optional.
87 for (samplenum, (miso, mosi, sck, cs)) in data:
89 self.samplenum += 1 # FIXME
91 # Ignore sample if the clock pin hasn't changed.
92 if sck == self.oldsck:
97 # Sample data on rising/falling clock edge (depends on mode).
98 mode = spi_mode[self.options['cpol'], self.options['cpha']]
99 if mode == 0 and sck == 0: # Sample on rising clock edge
101 elif mode == 1 and sck == 1: # Sample on falling clock edge
103 elif mode == 2 and sck == 1: # Sample on falling clock edge
105 elif mode == 3 and sck == 0: # Sample on rising clock edge
108 # If this is the first bit, save its sample number.
109 if self.bitcount == 0:
110 self.start_sample = samplenum
111 active_low = (self.options['cs_polarity'] == 'active-low')
112 deasserted = cs if active_low else not cs
114 self.cs_was_deasserted_during_data_word = 1
116 ws = self.options['wordsize']
118 # Receive MOSI bit into our shift register.
119 if self.options['bitorder'] == 'msb-first':
120 self.mosidata |= mosi << (ws - 1 - self.bitcount)
122 self.mosidata |= mosi << self.bitcount
124 # Receive MISO bit into our shift register.
125 if self.options['bitorder'] == 'msb-first':
126 self.misodata |= miso << (ws - 1 - self.bitcount)
128 self.misodata |= miso << self.bitcount
132 # Continue to receive if not enough bits were received, yet.
133 if self.bitcount != ws:
136 self.put(self.start_sample, self.samplenum, self.out_proto,
137 ['data', self.mosidata, self.misodata])
138 self.put(self.start_sample, self.samplenum, self.out_ann,
139 [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
142 if self.cs_was_deasserted_during_data_word:
143 self.put(self.start_sample, self.samplenum, self.out_ann,
144 [ANN_HEX, ['WARNING: CS# was deasserted during this '
147 # Reset decoder state.
152 # Keep stats for summary.
153 self.bytesreceived += 1