2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # SPI protocol decoder
24 import sigrokdecode as srd
26 # Key: (CPOL, CPHA). Value: SPI mode.
27 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
28 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
36 class Decoder(srd.Decoder):
40 longname = 'Serial Peripheral Interface'
41 desc = 'Full-duplex, synchronous, serial bus.'
46 {'id': 'miso', 'name': 'MISO',
47 'desc': 'SPI MISO line (Master in, slave out)'},
48 {'id': 'mosi', 'name': 'MOSI',
49 'desc': 'SPI MOSI line (Master out, slave in)'},
50 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
51 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
53 optional_probes = [] # TODO
55 'cs_polarity': ['CS# polarity', 'active-low'],
56 'cpol': ['Clock polarity', 0],
57 'cpha': ['Clock phase', 0],
58 'bitorder': ['Bit order within the SPI data', 'msb-first'],
59 'wordsize': ['Word size of SPI data', 8], # 1-64?
60 'format': ['Data format', 'hex'],
63 ['MISO/MOSI data', 'MISO/MOSI SPI data'],
64 ['MISO data', 'MISO SPI data'],
65 ['MOSI data', 'MOSI SPI data'],
66 ['Warnings', 'Human-readable warnings'],
74 self.bytesreceived = 0
77 self.cs_was_deasserted_during_data_word = 0
81 def start(self, metadata):
82 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
83 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
86 return 'SPI: %d bytes received' % self.bytesreceived
88 def putpw(self, data):
89 self.put(self.startsample, self.samplenum, self.out_proto, data)
92 self.put(self.startsample, self.samplenum, self.out_ann, data)
94 def decode(self, ss, es, data):
95 # TODO: Either MISO or MOSI could be optional. CS# is optional.
96 for (self.samplenum, pins) in data:
98 # Ignore identical samples early on (for performance reasons).
99 if self.oldpins == pins:
101 self.oldpins, (miso, mosi, sck, cs) = pins, pins
104 # Send all CS# pin value changes.
105 self.put(self.samplenum, self.samplenum, self.out_proto,
106 ['CS-CHANGE', self.oldcs, cs])
109 # Ignore sample if the clock pin hasn't changed.
110 if sck == self.oldsck:
115 # Sample data on rising/falling clock edge (depends on mode).
116 mode = spi_mode[self.options['cpol'], self.options['cpha']]
117 if mode == 0 and sck == 0: # Sample on rising clock edge
119 elif mode == 1 and sck == 1: # Sample on falling clock edge
121 elif mode == 2 and sck == 1: # Sample on falling clock edge
123 elif mode == 3 and sck == 0: # Sample on rising clock edge
126 # If this is the first bit, save its sample number.
127 if self.bitcount == 0:
128 self.startsample = self.samplenum
129 active_low = (self.options['cs_polarity'] == 'active-low')
130 deasserted = cs if active_low else not cs
132 self.cs_was_deasserted_during_data_word = 1
134 ws = self.options['wordsize']
136 # Receive MOSI bit into our shift register.
137 if self.options['bitorder'] == 'msb-first':
138 self.mosidata |= mosi << (ws - 1 - self.bitcount)
140 self.mosidata |= mosi << self.bitcount
142 # Receive MISO bit into our shift register.
143 if self.options['bitorder'] == 'msb-first':
144 self.misodata |= miso << (ws - 1 - self.bitcount)
146 self.misodata |= miso << self.bitcount
150 # Continue to receive if not enough bits were received, yet.
151 if self.bitcount != ws:
154 self.putpw(['DATA', self.mosidata, self.misodata])
155 self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
156 self.putw([1, ['%02X' % self.misodata]])
157 self.putw([2, ['%02X' % self.mosidata]])
159 if self.cs_was_deasserted_during_data_word:
160 self.putw([3, ['CS# was deasserted during this data word!']])
162 # Reset decoder state.
167 # Keep stats for summary.
168 self.bytesreceived += 1