2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
28 [<cmd>, <data1>, <data2>]
31 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
32 The data is _usually_ 8 bits (but can also be fewer or more bits).
33 Both data items are Python numbers (not strings), or None if the respective
34 probe was not supplied.
35 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
36 Both data items are Python numbers (0/1), not strings.
47 # Key: (CPOL, CPHA). Value: SPI mode.
48 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
49 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
57 class Decoder(srd.Decoder):
61 longname = 'Serial Peripheral Interface'
62 desc = 'Full-duplex, synchronous, serial bus.'
67 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
70 {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
71 {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
72 {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
75 'cs_polarity': ['CS# polarity', 'active-low'],
76 'cpol': ['Clock polarity', 0],
77 'cpha': ['Clock phase', 0],
78 'bitorder': ['Bit order within the SPI data', 'msb-first'],
79 'wordsize': ['Word size of SPI data', 8], # 1-64?
80 'format': ['Data format', 'hex'],
83 ['miso-data', 'MISO SPI data'],
84 ['mosi-data', 'MOSI SPI data'],
85 ['warnings', 'Human-readable warnings'],
88 ('miso', 'MISO', (0,)),
89 ('mosi', 'MOSI', (1,)),
90 ('other', 'Other', (2,)),
94 self.samplerate = None
101 self.cs_was_deasserted_during_data_word = 0
105 self.have_miso = None
106 self.have_mosi = None
109 def metadata(self, key, value):
110 if key == srd.SRD_CONF_SAMPLERATE:
111 self.samplerate = value
114 self.out_python = self.register(srd.OUTPUT_PYTHON)
115 self.out_ann = self.register(srd.OUTPUT_ANN)
116 self.out_bitrate = self.register(srd.OUTPUT_META,
117 meta=(int, 'Bitrate', 'Bitrate during transfers'))
119 def putpw(self, data):
120 self.put(self.startsample, self.samplenum, self.out_python, data)
122 def putw(self, data):
123 self.put(self.startsample, self.samplenum, self.out_ann, data)
125 def handle_bit(self, miso, mosi, clk, cs):
126 # If this is the first bit, save its sample number.
127 if self.bitcount == 0:
128 self.startsample = self.samplenum
130 active_low = (self.options['cs_polarity'] == 'active-low')
131 deasserted = cs if active_low else not cs
133 self.cs_was_deasserted_during_data_word = 1
135 ws = self.options['wordsize']
137 # Receive MOSI bit into our shift register.
139 if self.options['bitorder'] == 'msb-first':
140 self.mosidata |= mosi << (ws - 1 - self.bitcount)
142 self.mosidata |= mosi << self.bitcount
144 # Receive MISO bit into our shift register.
146 if self.options['bitorder'] == 'msb-first':
147 self.misodata |= miso << (ws - 1 - self.bitcount)
149 self.misodata |= miso << self.bitcount
153 # Continue to receive if not enough bits were received, yet.
154 if self.bitcount != ws:
157 si = self.mosidata if self.have_mosi else None
158 so = self.misodata if self.have_miso else None
160 # Pass MOSI and MISO to the next PD up the stack.
161 self.putpw(['DATA', si, so])
165 self.putw([0, ['%02X' % self.misodata]])
167 self.putw([1, ['%02X' % self.mosidata]])
170 elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
171 bitrate = int(1 / elapsed * self.options['wordsize'])
172 self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
174 if self.have_cs and self.cs_was_deasserted_during_data_word:
175 self.putw([2, ['CS# was deasserted during this data word!']])
177 # Reset decoder state.
178 self.misodata = 0 if self.have_miso else None
179 self.mosidata = 0 if self.have_mosi else None
182 def find_clk_edge(self, miso, mosi, clk, cs):
183 if self.have_cs and self.oldcs != cs:
184 # Send all CS# pin value changes.
185 self.put(self.samplenum, self.samplenum, self.out_python,
186 ['CS-CHANGE', self.oldcs, cs])
188 # Reset decoder state when CS# changes (and the CS# pin is used).
189 self.misodata = 0 if self.have_miso else None
190 self.mosidata = 0 if self.have_mosi else None
193 # Ignore sample if the clock pin hasn't changed.
194 if clk == self.oldclk:
199 # Sample data on rising/falling clock edge (depends on mode).
200 mode = spi_mode[self.options['cpol'], self.options['cpha']]
201 if mode == 0 and clk == 0: # Sample on rising clock edge
203 elif mode == 1 and clk == 1: # Sample on falling clock edge
205 elif mode == 2 and clk == 1: # Sample on falling clock edge
207 elif mode == 3 and clk == 0: # Sample on rising clock edge
210 # Found the correct clock edge, now get the SPI bit(s).
211 self.handle_bit(miso, mosi, clk, cs)
213 def decode(self, ss, es, data):
214 if self.samplerate is None:
215 raise Exception("Cannot decode without samplerate.")
216 # Either MISO or MOSI can be omitted (but not both). CS# is optional.
217 for (self.samplenum, pins) in data:
219 # Ignore identical samples early on (for performance reasons).
220 if self.oldpins == pins:
222 self.oldpins, (clk, miso, mosi, cs) = pins, pins
223 self.have_miso = (miso in (0, 1))
224 self.have_mosi = (mosi in (0, 1))
225 self.have_cs = (cs in (0, 1))
228 if self.state == 'IDLE':
229 self.find_clk_edge(miso, mosi, clk, cs)
231 raise Exception('Invalid state: %s' % self.state)