2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # SPI protocol decoder
24 import sigrokdecode as srd
27 Protocol output format:
30 [<cmd>, <data1>, <data2>]
33 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
34 The data is _usually_ 8 bits (but can also be fewer or more bits).
35 Both data items are Python numbers, not strings.
36 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
37 Both data items are Python numbers (0/1), not strings.
46 # Key: (CPOL, CPHA). Value: SPI mode.
47 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
48 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
56 class Decoder(srd.Decoder):
60 longname = 'Serial Peripheral Interface'
61 desc = 'Full-duplex, synchronous, serial bus.'
66 {'id': 'miso', 'name': 'MISO',
67 'desc': 'SPI MISO line (Master in, slave out)'},
68 {'id': 'mosi', 'name': 'MOSI',
69 'desc': 'SPI MOSI line (Master out, slave in)'},
70 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
73 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
76 'cs_polarity': ['CS# polarity', 'active-low'],
77 'cpol': ['Clock polarity', 0],
78 'cpha': ['Clock phase', 0],
79 'bitorder': ['Bit order within the SPI data', 'msb-first'],
80 'wordsize': ['Word size of SPI data', 8], # 1-64?
81 'format': ['Data format', 'hex'],
84 ['MISO/MOSI data', 'MISO/MOSI SPI data'],
85 ['MISO data', 'MISO SPI data'],
86 ['MOSI data', 'MOSI SPI data'],
87 ['Warnings', 'Human-readable warnings'],
95 self.bytesreceived = 0
98 self.cs_was_deasserted_during_data_word = 0
103 def start(self, metadata):
104 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
105 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
108 return 'SPI: %d bytes received' % self.bytesreceived
110 def putpw(self, data):
111 self.put(self.startsample, self.samplenum, self.out_proto, data)
113 def putw(self, data):
114 self.put(self.startsample, self.samplenum, self.out_ann, data)
116 def handle_bit(self, miso, mosi, sck, cs):
117 # If this is the first bit, save its sample number.
118 if self.bitcount == 0:
119 self.startsample = self.samplenum
121 active_low = (self.options['cs_polarity'] == 'active-low')
122 deasserted = cs if active_low else not cs
124 self.cs_was_deasserted_during_data_word = 1
126 ws = self.options['wordsize']
128 # Receive MOSI bit into our shift register.
129 if self.options['bitorder'] == 'msb-first':
130 self.mosidata |= mosi << (ws - 1 - self.bitcount)
132 self.mosidata |= mosi << self.bitcount
134 # Receive MISO bit into our shift register.
135 if self.options['bitorder'] == 'msb-first':
136 self.misodata |= miso << (ws - 1 - self.bitcount)
138 self.misodata |= miso << self.bitcount
142 # Continue to receive if not enough bits were received, yet.
143 if self.bitcount != ws:
146 self.putpw(['DATA', self.mosidata, self.misodata])
147 self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
148 self.putw([1, ['%02X' % self.misodata]])
149 self.putw([2, ['%02X' % self.mosidata]])
151 if self.cs_was_deasserted_during_data_word:
152 self.putw([3, ['CS# was deasserted during this data word!']])
154 # Reset decoder state.
155 self.mosidata = self.misodata = self.bitcount = 0
157 # Keep stats for summary.
158 self.bytesreceived += 1
160 def find_clk_edge(self, miso, mosi, sck, cs):
161 if self.have_cs and self.oldcs != cs:
162 # Send all CS# pin value changes.
163 self.put(self.samplenum, self.samplenum, self.out_proto,
164 ['CS-CHANGE', self.oldcs, cs])
166 # Reset decoder state when CS# changes (and the CS# pin is used).
167 self.mosidata = self.misodata = self.bitcount= 0
169 # Ignore sample if the clock pin hasn't changed.
170 if sck == self.oldsck:
175 # Sample data on rising/falling clock edge (depends on mode).
176 mode = spi_mode[self.options['cpol'], self.options['cpha']]
177 if mode == 0 and sck == 0: # Sample on rising clock edge
179 elif mode == 1 and sck == 1: # Sample on falling clock edge
181 elif mode == 2 and sck == 1: # Sample on falling clock edge
183 elif mode == 3 and sck == 0: # Sample on rising clock edge
186 # Found the correct clock edge, now get the SPI bit(s).
187 self.handle_bit(miso, mosi, sck, cs)
189 def decode(self, ss, es, data):
190 # TODO: Either MISO or MOSI could be optional. CS# is optional.
191 for (self.samplenum, pins) in data:
193 # Ignore identical samples early on (for performance reasons).
194 if self.oldpins == pins:
196 self.oldpins, (miso, mosi, sck, cs) = pins, pins
197 self.have_cs = (cs in (0, 1))
200 if self.state == 'IDLE':
201 self.find_clk_edge(miso, mosi, sck, cs)
203 raise Exception('Invalid state: %s' % self.state)