2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
28 [<ptype>, <data1>, <data2>]
31 - 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data.
32 The data is _usually_ 8 bits (but can also be fewer or more bits).
33 Both data items are Python numbers (not strings), or None if the respective
34 channel was not supplied.
35 - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data
36 item, and for each of those also their respective start-/endsample numbers.
37 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
38 Both data items are Python numbers (0/1), not strings. At the beginning of
39 the decoding a packet is generated with <data1> = None and <data2> being the
40 initial state of the CS# pin or None if the chip select pin is not supplied.
43 ['CS-CHANGE', None, 1]
46 ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
47 [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]],
48 [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88],
49 [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]]
56 # Key: (CPOL, CPHA). Value: SPI mode.
57 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
58 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
66 class SamplerateError(Exception):
69 class ChannelError(Exception):
72 class Decoder(srd.Decoder):
76 longname = 'Serial Peripheral Interface'
77 desc = 'Full-duplex, synchronous, serial bus.'
82 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
85 {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
86 {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
87 {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
90 {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
91 'values': ('active-low', 'active-high')},
92 {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0,
94 {'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
96 {'id': 'bitorder', 'desc': 'Bit order',
97 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
98 {'id': 'wordsize', 'desc': 'Word size', 'default': 8},
101 ('miso-data', 'MISO data'),
102 ('mosi-data', 'MOSI data'),
103 ('miso-bits', 'MISO bits'),
104 ('mosi-bits', 'MOSI bits'),
105 ('warnings', 'Human-readable warnings'),
108 ('miso-data', 'MISO data', (0,)),
109 ('miso-bits', 'MISO bits', (2,)),
110 ('mosi-data', 'MOSI data', (1,)),
111 ('mosi-bits', 'MOSI bits', (3,)),
112 ('other', 'Other', (4,)),
120 self.samplerate = None
123 self.misodata = self.mosidata = 0
128 self.cs_was_deasserted = False
131 self.have_cs = self.have_miso = self.have_mosi = None
132 self.no_cs_notification = False
134 def metadata(self, key, value):
135 if key == srd.SRD_CONF_SAMPLERATE:
136 self.samplerate = value
139 self.out_python = self.register(srd.OUTPUT_PYTHON)
140 self.out_ann = self.register(srd.OUTPUT_ANN)
141 self.out_bin = self.register(srd.OUTPUT_BINARY)
142 self.out_bitrate = self.register(srd.OUTPUT_META,
143 meta=(int, 'Bitrate', 'Bitrate during transfers'))
145 def putw(self, data):
146 self.put(self.ss_block, self.samplenum, self.out_ann, data)
149 # Pass MISO and MOSI bits and then data to the next PD up the stack.
150 so = self.misodata if self.have_miso else None
151 si = self.mosidata if self.have_mosi else None
152 so_bits = self.misobits if self.have_miso else None
153 si_bits = self.mosibits if self.have_mosi else None
156 ss, es = self.misobits[-1][1], self.misobits[0][2]
157 self.put(ss, es, self.out_bin, (0, bytes([so])))
159 ss, es = self.mosibits[-1][1], self.mosibits[0][2]
160 self.put(ss, es, self.out_bin, (1, bytes([si])))
162 self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
163 self.put(ss, es, self.out_python, ['DATA', si, so])
167 for bit in self.misobits:
168 self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]])
170 for bit in self.mosibits:
171 self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]])
173 # Dataword annotations.
175 self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
177 self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
179 def reset_decoder_state(self):
180 self.misodata = 0 if self.have_miso else None
181 self.mosidata = 0 if self.have_mosi else None
182 self.misobits = [] if self.have_miso else None
183 self.mosibits = [] if self.have_mosi else None
186 def cs_asserted(self, cs):
187 active_low = (self.options['cs_polarity'] == 'active-low')
188 return (cs == 0) if active_low else (cs == 1)
190 def handle_bit(self, miso, mosi, clk, cs):
191 # If this is the first bit of a dataword, save its sample number.
192 if self.bitcount == 0:
193 self.ss_block = self.samplenum
194 self.cs_was_deasserted = \
195 not self.cs_asserted(cs) if self.have_cs else False
197 ws = self.options['wordsize']
199 # Receive MISO bit into our shift register.
201 if self.options['bitorder'] == 'msb-first':
202 self.misodata |= miso << (ws - 1 - self.bitcount)
204 self.misodata |= miso << self.bitcount
206 # Receive MOSI bit into our shift register.
208 if self.options['bitorder'] == 'msb-first':
209 self.mosidata |= mosi << (ws - 1 - self.bitcount)
211 self.mosidata |= mosi << self.bitcount
213 # Guesstimate the endsample for this bit (can be overridden below).
215 if self.bitcount > 0:
217 es += self.samplenum - self.misobits[0][1]
219 es += self.samplenum - self.mosibits[0][1]
222 self.misobits.insert(0, [miso, self.samplenum, es])
224 self.mosibits.insert(0, [mosi, self.samplenum, es])
226 if self.bitcount > 0 and self.have_miso:
227 self.misobits[1][2] = self.samplenum
228 if self.bitcount > 0 and self.have_mosi:
229 self.mosibits[1][2] = self.samplenum
233 # Continue to receive if not enough bits were received, yet.
234 if self.bitcount != ws:
240 elapsed = 1 / float(self.samplerate)
241 elapsed *= (self.samplenum - self.ss_block + 1)
242 bitrate = int(1 / elapsed * self.options['wordsize'])
243 self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
245 if self.have_cs and self.cs_was_deasserted:
246 self.putw([4, ['CS# was deasserted during this data word!']])
248 self.reset_decoder_state()
250 def find_clk_edge(self, miso, mosi, clk, cs):
251 if self.have_cs and self.oldcs != cs:
252 # Send all CS# pin value changes.
253 self.put(self.samplenum, self.samplenum, self.out_python,
254 ['CS-CHANGE', self.oldcs, cs])
256 # Reset decoder state when CS# changes (and the CS# pin is used).
257 self.reset_decoder_state()
259 # We only care about samples if CS# is asserted.
260 if self.have_cs and not self.cs_asserted(cs):
263 # Ignore sample if the clock pin hasn't changed.
264 if clk == self.oldclk:
269 # Sample data on rising/falling clock edge (depends on mode).
270 mode = spi_mode[self.options['cpol'], self.options['cpha']]
271 if mode == 0 and clk == 0: # Sample on rising clock edge
273 elif mode == 1 and clk == 1: # Sample on falling clock edge
275 elif mode == 2 and clk == 1: # Sample on falling clock edge
277 elif mode == 3 and clk == 0: # Sample on rising clock edge
280 # Found the correct clock edge, now get the SPI bit(s).
281 self.handle_bit(miso, mosi, clk, cs)
283 def decode(self, ss, es, data):
284 if not self.samplerate:
285 raise SamplerateError('Cannot decode without samplerate.')
286 # Either MISO or MOSI can be omitted (but not both). CS# is optional.
287 for (self.samplenum, pins) in data:
289 # Ignore identical samples early on (for performance reasons).
290 if self.oldpins == pins:
292 self.oldpins, (clk, miso, mosi, cs) = pins, pins
293 self.have_miso = (miso in (0, 1))
294 self.have_mosi = (mosi in (0, 1))
295 self.have_cs = (cs in (0, 1))
297 # Either MISO or MOSI (but not both) can be omitted.
298 if not (self.have_miso or self.have_mosi):
299 raise ChannelError('Either MISO or MOSI (or both) pins required.')
301 # Tell stacked decoders that we don't have a CS# signal.
302 if not self.no_cs_notification and not self.have_cs:
303 self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
304 self.no_cs_notification = True
306 self.find_clk_edge(miso, mosi, clk, cs)