2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
28 # Clock polarity options
29 CPOL_0 = 0 # Clock is low when inactive
30 CPOL_1 = 1 # Clock is high when inactive
33 CPHA_0 = 0 # Data is valid on the rising clock edge
34 CPHA_1 = 1 # Data is valid on the falling clock edge
43 class Decoder(srd.Decoder):
46 longname = 'Serial Peripheral Interface (SPI) bus'
48 longdesc = '...longdesc...'
49 author = 'Gareth McMullin'
50 email = 'gareth@blacksphere.co.nz'
55 {'id': 'mosi', 'name': 'MOSI',
56 'desc': 'SPI MOSI line (Master out, slave in)'},
57 {'id': 'miso', 'name': 'MISO',
58 'desc': 'SPI MISO line (Master in, slave out)'},
59 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
60 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
63 'cs_active_low': ['CS# active low', ACTIVE_LOW],
64 'clock_polarity': ['Clock polarity', CPOL_0],
65 'clock_phase': ['Clock phase', CPHA_0],
66 'bit_order': ['Bit order within the SPI data', MSB_FIRST],
67 'word_size': ['Word size of SPI data', 8], # 1-64?
70 ['Hex', 'SPI data bytes in hex format'],
78 self.bytesreceived = 0
81 def start(self, metadata):
82 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
83 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
86 return 'SPI: %d bytes received' % self.bytesreceived
88 def decode(self, ss, es, data):
89 # HACK! At the moment the number of probes is not handled correctly.
90 # E.g. if an input file (-i foo.sr) has more than two probes enabled.
91 # for (samplenum, (mosi, sck, x, y, z, a)) in data:
92 # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
93 for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
95 self.samplenum += 1 # FIXME
97 # Sample data on rising SCK edges.
98 if sck == self.oldsck:
104 # If this is the first bit, save its sample number.
105 if self.bitcount == 0:
106 self.start_sample = samplenum
108 # Receive bit into our shift register.
110 self.mosidata |= 1 << (7 - self.bitcount)
112 self.misodata |= 1 << (7 - self.bitcount)
116 # Continue to receive if not a byte yet.
117 if self.bitcount != 8:
120 self.put(self.start_sample, self.samplenum, self.out_proto,
121 ['data', self.mosidata, self.misodata])
122 self.put(self.start_sample, self.samplenum, self.out_ann,
123 [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
126 # Reset decoder state.
131 # Keep stats for summary.
132 self.bytesreceived += 1