2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2019 Federico Cerutti <federico@ceres-c.it>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 from common.srdhelper import bitpack_lsb
21 import sigrokdecode as srd
24 RST, CLK, IO, = range(3)
27 BIT, ATR, CMD, DATA, RESET, = range(5)
32 # CMD: [annotation class index, annotation texts for zoom levels]
34 'BIT': [Ann.BIT, '{bit}',],
35 'ATR': [Ann.ATR, 'Answer To Reset: {data:02x}', 'ATR: {data:02x}', '{data:02x}',],
36 'CMD': [Ann.CMD, 'Command: {data:02x}', 'Cmd: {data:02x}', '{data:02x}',],
37 'DATA': [Ann.DATA, 'Data: {data:02x}', '{data:02x}',],
38 'RESET': [Ann.RESET, 'Reset', 'R',],
41 def lookup_proto_ann_txt(cmd, variables):
42 ann = proto.get(cmd, None)
45 cls, texts = ann[0], ann[1:]
46 texts = [t.format(**variables) for t in texts]
49 class Decoder(srd.Decoder):
53 longname = 'SLE44xx memory card'
54 desc = 'SLE 4418/28/32/42 memory card serial protocol'
60 {'id': 'rst', 'name': 'RST', 'desc': 'Reset line'},
61 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
62 {'id': 'io', 'name': 'I/O', 'desc': 'I/O data line'},
68 ('data', 'Data exchange'),
72 ('bits', 'Bits', (Ann.BIT,)),
73 ('fields', 'Fields', (Ann.ATR, Ann.CMD, Ann.DATA)),
74 ('interrupts', 'Interrupts', (Ann.RESET,)),
77 ('send-data', 'Send data'),
87 def metadata(self, key, value):
88 if key == srd.SRD_CONF_SAMPLERATE:
89 self.samplerate = value
92 self.out_ann = self.register(srd.OUTPUT_ANN)
93 self.out_binary = self.register(srd.OUTPUT_BINARY)
95 def putx(self, ss, es, cls, data):
96 self.put(ss, es, self.out_ann, [cls, data,])
98 def putb(self, ss, es, cls , data):
99 self.put(ss, es, self.out_binary, [cls, data,])
101 def handle_reset(self, pins):
103 cls, texts = lookup_proto_ann_txt(self.cmd, {})
104 self.putx(self.samplenum, self.samplenum, cls, texts)
106 # Next data bytes will be Answer To Reset.
109 def handle_command(self, pins):
111 # XXX Is the comment inverted?
112 # If I/O is rising -> command START
113 # if I/O is falling -> command STOP and response data incoming
114 self.cmd = 'CMD' if io == 0 else 'DATA'
117 # Gather 8 bits of data
118 def handle_data(self, pins):
121 # Remember the start of the first data/address bit. Collect
122 # bits in LSB first order. "Estimate" the bit's width at first,
123 # update end times as better data becomes available.
124 # TODO This estimation logic is imprecise and fragile. A single
125 # slightly stretched clock period throws off the following bit
126 # annotation. Better look for more reliable conditions. Available
127 # documentation suggests bit values are valid during high CLK.
129 bit_ss = self.samplenum
130 bit_es = bit_ss # self.bitwidth is not known yet.
132 self.bits[-1][2] = bit_ss
133 self.bits.append([bit_val, bit_ss, bit_es])
134 if len(self.bits) < 8:
136 bitwidth = self.bits[-1][1] - self.bits[-2][1]
137 self.bits[-1][2] += bitwidth
139 # Get the data byte value, and byte's ss/es.
140 databyte = bitpack_lsb(self.bits, 0)
141 byte_ss = self.bits[0][1]
142 byte_es = self.bits[-1][2]
144 self.putb(byte_ss, byte_es, Bin.SEND_DATA, bytes([databyte]))
146 # TODO Present bit values earlier. As soon as their es is known.
147 for bit_val, bit_ss, bit_es in self.bits:
148 cls, texts = lookup_proto_ann_txt('BIT', {'bit': bit_val})
149 self.putx(bit_ss, bit_es, cls, texts)
151 cls, texts = lookup_proto_ann_txt(self.cmd, {'data': databyte})
153 self.putx(byte_ss, byte_es, cls, texts)
155 # Done with this packet.
160 # Signal conditions tracked by the protocol decoder:
161 # - RESET condition (R): RST = rising
162 # - Incoming data (D): RST = low, CLK = rising.
163 # TODO Add "RST low, CLK fall" for "end of DATA" here?
164 # - Command mode START: CLK = high, I/O = falling.
165 # - Command mode STOP: CLK = high, I/O = rising.
166 (COND_RESET, COND_DATA, COND_CMD_START, COND_CMD_STOP,) = range(4)
169 {Pin.RST: 'l', Pin.CLK: 'r'},
170 {Pin.CLK: 'h', Pin.IO: 'f'},
171 {Pin.CLK: 'h', Pin.IO: 'r'},
173 pins = self.wait(conditions)
174 if self.matched[COND_RESET]:
175 self.handle_reset(pins)
176 elif self.matched[COND_DATA]:
177 self.handle_data(pins)
178 elif self.matched[COND_CMD_START]:
179 self.handle_command(pins)
180 elif self.matched[COND_CMD_STOP]:
181 self.handle_command(pins)