2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2019 Shirow Miura <shirowmiura@gmail.com>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
41 START, STOP, CLOCK, DATA = range(4)
43 class Decoder(srd.Decoder):
47 longname = 'Signature analysis'
48 desc = 'Annotate signature of logic patterns.'
52 tags = ['Debug/trace', 'Util', 'Encoding']
54 dict(id='start', name='START', desc='START channel'),
55 dict(id='stop', name='STOP', desc='STOP channel'),
56 dict(id='clk', name='CLOCK', desc='CLOCK channel'),
57 dict(id='data', name='DATA', desc='DATA channel')
60 dict(id='start_edge', desc='Edge-selection for START channel',
61 default='r', values=('r', 'f')),
62 dict(id='stop_edge', desc='Edge-selection for STOP channel',
63 default='r', values=('r', 'f')),
64 dict(id='clk_edge', desc='Edge-selection for CLOCK channel',
65 default='f', values=('r', 'f')),
66 dict(id='annbits', desc='Enable bit level annotation',
67 default='no', values=('yes', 'no'))
77 ('bits', 'Bits', (0, 1, 2, 3)),
85 self.out_ann = self.register(srd.OUTPUT_ANN)
87 def putsig(self, ss, es, signature):
88 s = ''.join([symbol_map[(signature >> 0) & 0x0f],
89 symbol_map[(signature >> 4) & 0x0f],
90 symbol_map[(signature >> 8) & 0x0f],
91 symbol_map[(signature >> 12) & 0x0f]])
92 self.put(ss, es, self.out_ann, [4, [s]])
94 def putb(self, ss, ann):
95 self.put(ss, self.samplenum, self.out_ann, ann)
99 start_edge_mode_rising = opt['start_edge'] == 'r'
100 stop_edge_mode_rising = opt['stop_edge'] == 'r'
101 annbits = opt['annbits'] == 'yes'
106 prev_start = 0 if start_edge_mode_rising else 1
107 prev_stop = 0 if stop_edge_mode_rising else 1
111 start, stop, _, data = self.wait({CLOCK: opt['clk_edge']})
112 if start != prev_start and not gate_is_open:
113 gate_is_open = (start == 1) if start_edge_mode_rising else (start == 0)
116 sample_start = self.samplenum
118 elif stop != prev_stop and gate_is_open:
119 gate_is_open = not ((stop == 1) if stop_edge_mode_rising else (stop == 0))
123 self.putb(last_samplenum, [3, ['STOP', 'STP', 'P']])
124 self.putsig(sample_start, self.samplenum, shiftreg)
130 s = '<{}>'.format(data)
131 self.putb(last_samplenum, [2, ['START' + s, 'STR' + s, 'S' + s]])
134 self.putb(last_samplenum, [data, [str(data)]])
135 incoming = (bin(shiftreg & 0b0000_0010_1001_0001).count('1') + data) & 1
136 shiftreg = (incoming << 15) | (shiftreg >> 1)
139 last_samplenum = self.samplenum