2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2020 Analog Devices Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 3 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
23 0x00: ['GND', 'GND', 'GND', 'G'],
24 0x01: ['FLOAT', 'FLOAT', 'FLOAT', 'F'],
25 0x02: ['VCC', 'VCC', 'VCC', 'V'],
29 0x00: ['Write Input Register', 'Write In Reg', 'Wr In Reg', 'WIR'],
30 0x01: ['Update DAC', 'Update', 'U'],
31 0x03: ['Write and Power Up DAC', 'Write & Power Up', 'W&PU'],
32 0x04: ['Power Down DAC', 'Power Down', 'PD'],
33 0x0F: ['No Operation', 'No Op', 'NO'],
39 0x0F: ['All DACs', 'All'],
42 input_voltage_format = ['%fV', '%fV', '%.6fV', '%.2fV']
44 class Decoder(srd.Decoder):
48 longname = 'Linear Technology LTC26x7'
49 desc = 'Linear Technology LTC26x7 16-/14-/12-bit rail-to-rail DACs.'
53 tags = ['IC', 'Analog/digital']
55 {'id': 'part', 'desc': 'Part', 'default': 'ltc26x7',
56 'values': ('ltc2607', 'ltc2617', 'ltc2627')},
57 {'id': 'ref', 'desc': 'Reference voltage', 'default': 1.5},
60 ('slave_addr', 'Slave address'),
61 ('command', 'Command'),
62 ('address', 'Address'),
63 ('data', '2 byte data'),
75 self.out_ann = self.register(srd.OUTPUT_ANN)
77 def convert_ternary_str(self, n):
86 return list(reversed(nums))
88 def handle_slave_addr(self, data):
90 ann = ['Global address', 'Global addr', 'Glob addr', 'GA']
91 self.put(self.ss, self.es, self.out_ann, [0, ann])
93 ann = ['CA2=%s CA1=%s CA0=%s', '2=%s 1=%s 0=%s', '%s %s %s', '%s %s %s']
107 ternary_values = self.convert_ternary_str(addr)
108 for i in range(len(ann)):
109 ann[i] = ann[i] % (slave_address[ternary_values[0]][i],
110 slave_address[ternary_values[1]][i],
111 slave_address[ternary_values[2]][i])
112 self.put(self.ss, self.es, self.out_ann, [0, ann])
114 def handle_cmd_addr(self, data):
115 cmd_val = (data >> 4) & 0x0F
116 dac_val = (data & 0x0F)
117 sm = (self.ss + self.es) // 2
119 self.put(self.ss, sm, self.out_ann, [1, commands[cmd_val]])
120 self.put(sm, self.es, self.out_ann, [2, addresses[dac_val]])
122 def handle_data(self, data):
123 self.data = (self.data << 8) & 0xFF00
125 if self.options['part'] == 'ltc2617':
126 self.data = (self.data >> 2)
127 self.data = (self.options['ref'] * self.data) / 0x3FFF
128 elif self.options['part'] == 'ltc2627':
129 self.data = (self.data >> 4)
130 self.data = (self.options['ref'] * self.data) / 0x0FFF
132 self.data = (self.options['ref'] * self.data) / 0xFFFF
134 for format in input_voltage_format:
135 ann.append(format % self.data)
138 self.put(self.ss, self.es, self.out_ann, [3, ann])
140 def decode(self, ss, es, data):
145 if self.state == 'IDLE':
146 # Wait for an I²C START condition.
149 self.state = 'GET SLAVE ADDR'
150 elif self.state == 'GET SLAVE ADDR':
151 # Wait for an address write operation.
152 if cmd != 'ADDRESS WRITE':
155 self.handle_slave_addr(databyte)
157 self.state = 'GET CMD ADDR'
158 elif self.state == 'GET CMD ADDR':
159 if cmd != 'DATA WRITE':
162 self.handle_cmd_addr(databyte)
164 self.state = 'WRITE DATA'
165 elif self.state == 'WRITE DATA':
166 if cmd == 'DATA WRITE':
171 self.handle_data(databyte)