2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
29 - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
30 Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
31 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
32 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
33 'EXIT2-IR', 'UPDATE-IR'.
34 - 'IR TDI': Bitstring that was clocked into the IR register.
35 - 'IR TDO': Bitstring that was clocked out of the IR register.
36 - 'DR TDI': Bitstring that was clocked into the DR register.
37 - 'DR TDO': Bitstring that was clocked out of the DR register.
39 All bitstrings are a list consisting of two items. The first is a sequence
40 of '1' and '0' characters (the right-most character is the LSB. Example:
41 '01110001', where 1 is the LSB). The second item is a list of ss/es values
42 for each bit that is in the bitstring.
47 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
49 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
50 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
52 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
53 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
56 class Decoder(srd.Decoder):
60 longname = 'Joint Test Action Group (IEEE 1149.1)'
61 desc = 'Protocol for testing, debugging, and flashing ICs.'
66 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
67 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
68 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
69 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
72 {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
73 {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
74 {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
76 annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
77 ('bit-tdi', 'Bit (TDI)'),
78 ('bit-tdo', 'Bit (TDO)'),
79 ('bitstring-tdi', 'Bitstring (TDI)'),
80 ('bitstring-tdo', 'Bitstring (TDO)'),
83 ('bits-tdi', 'Bits (TDI)', (16,)),
84 ('bits-tdo', 'Bits (TDO)', (17,)),
85 ('bitstrings-tdi', 'Bitstring (TDI)', (18,)),
86 ('bitstrings-tdo', 'Bitstring (TDO)', (19,)),
87 ('states', 'States', tuple(range(15 + 1))),
91 # self.state = 'TEST-LOGIC-RESET'
92 self.state = 'RUN-TEST/IDLE'
96 self.bits_samplenums_tdi = []
97 self.bits_samplenums_tdo = []
98 self.ss_item = self.es_item = None
99 self.ss_bitstring = self.es_bitstring = None
100 self.saved_item = None
102 self.first_bit = True
105 self.out_python = self.register(srd.OUTPUT_PYTHON)
106 self.out_ann = self.register(srd.OUTPUT_ANN)
108 def putx(self, data):
109 self.put(self.ss_item, self.es_item, self.out_ann, data)
111 def putp(self, data):
112 self.put(self.ss_item, self.es_item, self.out_python, data)
114 def putx_bs(self, data):
115 self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
117 def putp_bs(self, data):
118 self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
120 def advance_state_machine(self, tms):
121 self.oldstate = self.state
124 if self.state == 'TEST-LOGIC-RESET':
125 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
126 elif self.state == 'RUN-TEST/IDLE':
127 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
130 elif self.state == 'SELECT-DR-SCAN':
131 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
132 elif self.state == 'CAPTURE-DR':
133 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
134 elif self.state == 'SHIFT-DR':
135 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
136 elif self.state == 'EXIT1-DR':
137 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
138 elif self.state == 'PAUSE-DR':
139 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
140 elif self.state == 'EXIT2-DR':
141 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
142 elif self.state == 'UPDATE-DR':
143 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
146 elif self.state == 'SELECT-IR-SCAN':
147 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
148 elif self.state == 'CAPTURE-IR':
149 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
150 elif self.state == 'SHIFT-IR':
151 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
152 elif self.state == 'EXIT1-IR':
153 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
154 elif self.state == 'PAUSE-IR':
155 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
156 elif self.state == 'EXIT2-IR':
157 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
158 elif self.state == 'UPDATE-IR':
159 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
161 def handle_rising_tck_edge(self, pins):
162 (tdi, tdo, tck, tms, trst, srst, rtck) = pins
164 # Rising TCK edges always advance the state machine.
165 self.advance_state_machine(tms)
168 # Save the start sample and item for later (no output yet).
169 self.ss_item = self.samplenum
172 # Output the saved item (from the last CLK edge to the current).
173 self.es_item = self.samplenum
174 # Output the old state (from last rising TCK edge to current one).
175 self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
176 self.putp(['NEW STATE', self.state])
178 # Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values.
179 if self.state.startswith('SHIFT-'):
181 self.ss_bitstring = self.samplenum
182 self.first_bit = False
184 self.putx([16, [str(self.bits_tdi[0])]])
185 self.putx([17, [str(self.bits_tdo[0])]])
186 # Use self.samplenum as ES of the previous bit.
187 self.bits_samplenums_tdi[0][1] = self.samplenum
188 self.bits_samplenums_tdo[0][1] = self.samplenum
190 self.bits_tdi.insert(0, tdi)
191 self.bits_tdo.insert(0, tdo)
193 # Use self.samplenum as SS of the current bit.
194 self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
195 self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
197 # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
198 if self.oldstate.startswith('SHIFT-') and \
199 self.state.startswith('EXIT1-'):
201 self.es_bitstring = self.samplenum
203 t = self.state[-2:] + ' TDI'
204 b = ''.join(map(str, self.bits_tdi))
205 h = ' (0x%x' % int('0b' + b, 2) + ')'
206 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
207 self.putx_bs([18, [s]])
208 self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit.
209 self.putp_bs([t, [b, self.bits_samplenums_tdi]])
210 self.putx([16, [str(self.bits_tdi[0])]]) # Last bit.
212 self.bits_samplenums_tdi = []
214 t = self.state[-2:] + ' TDO'
215 b = ''.join(map(str, self.bits_tdo))
216 h = ' (0x%x' % int('0b' + b, 2) + ')'
217 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
218 self.putx_bs([19, [s]])
219 self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit.
220 self.putp_bs([t, [b, self.bits_samplenums_tdo]])
221 self.putx([17, [str(self.bits_tdo[0])]]) # Last bit.
223 self.bits_samplenums_tdo = []
225 self.first_bit = True
227 self.ss_bitstring = self.samplenum
229 self.ss_item = self.samplenum
233 # Wait for a rising edge on TCK.
234 self.handle_rising_tck_edge(self.wait({2: 'r'}))