2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2010-2016 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
21 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
22 # TODO: Implement support for detecting various bus errors.
24 from common.srdhelper import bitpack_msb
25 import sigrokdecode as srd
34 - 'START' (START condition)
35 - 'START REPEAT' (Repeated START condition)
36 - 'ADDRESS READ' (Slave address, read)
37 - 'ADDRESS WRITE' (Slave address, write)
38 - 'DATA READ' (Data, read)
39 - 'DATA WRITE' (Data, write)
40 - 'STOP' (STOP condition)
43 - 'BITS' (<pdata>: list of data/address bits and their ss/es numbers)
45 <pdata> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
46 command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
47 For example, a slave address field could be 0x51 (instead of 0xa2).
48 For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <pdata> is None.
51 # Meaning of table items:
52 # command -> [annotation class, annotation text in order of decreasing length]
54 'START': [0, 'Start', 'S'],
55 'START REPEAT': [1, 'Start repeat', 'Sr'],
56 'STOP': [2, 'Stop', 'P'],
57 'ACK': [3, 'ACK', 'A'],
58 'NACK': [4, 'NACK', 'N'],
60 'ADDRESS READ': [6, 'Address read: {b:02X}', 'AR: {b:02X}', '{b:02X}'],
61 'ADDRESS WRITE': [7, 'Address write: {b:02X}', 'AW: {b:02X}', '{b:02X}'],
62 'DATA READ': [8, 'Data read: {b:02X}', 'DR: {b:02X}', '{b:02X}'],
63 'DATA WRITE': [9, 'Data write: {b:02X}', 'DW: {b:02X}', '{b:02X}'],
66 class Decoder(srd.Decoder):
70 longname = 'Inter-Integrated Circuit'
71 desc = 'Two-wire, multi-master, serial bus.'
75 tags = ['Embedded/industrial']
77 {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
78 {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
81 {'id': 'address_format', 'desc': 'Displayed slave address format',
82 'default': 'shifted', 'values': ('shifted', 'unshifted')},
85 ('start', 'Start condition'),
86 ('repeat-start', 'Repeat start condition'),
87 ('stop', 'Stop condition'),
90 ('bit', 'Data/address bit'),
91 ('address-read', 'Address read'),
92 ('address-write', 'Address write'),
93 ('data-read', 'Data read'),
94 ('data-write', 'Data write'),
95 ('warning', 'Warning'),
98 ('bits', 'Bits', (5,)),
99 ('addr-data', 'Address/data', (0, 1, 2, 3, 4, 6, 7, 8, 9)),
100 ('warnings', 'Warnings', (10,)),
103 ('address-read', 'Address read'),
104 ('address-write', 'Address write'),
105 ('data-read', 'Data read'),
106 ('data-write', 'Data write'),
113 self.samplerate = None
114 self.ss = self.es = self.ss_byte = -1
116 self.rem_addr_bytes = None
117 self.is_repeat_start = False
118 self.state = 'FIND START'
119 self.pdu_start = None
123 def metadata(self, key, value):
124 if key == srd.SRD_CONF_SAMPLERATE:
125 self.samplerate = value
128 self.out_python = self.register(srd.OUTPUT_PYTHON)
129 self.out_ann = self.register(srd.OUTPUT_ANN)
130 self.out_binary = self.register(srd.OUTPUT_BINARY)
131 self.out_bitrate = self.register(srd.OUTPUT_META,
132 meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))
134 def putx(self, data):
135 self.put(self.ss, self.es, self.out_ann, data)
137 def putp(self, data):
138 self.put(self.ss, self.es, self.out_python, data)
140 def putb(self, data):
141 self.put(self.ss, self.es, self.out_binary, data)
143 def handle_start(self, pins):
144 self.ss, self.es = self.samplenum, self.samplenum
145 if self.is_repeat_start:
149 self.pdu_start = self.samplenum
151 self.putp([cmd, None])
152 cls, texts = proto[cmd][0], proto[cmd][1:]
153 self.putx([cls, texts])
154 self.state = 'FIND ADDRESS'
155 self.is_repeat_start = True
157 self.rem_addr_bytes = None
158 self.data_bits.clear()
160 # Gather 8 bits of data plus the ACK/NACK bit.
161 def handle_address_or_data(self, pins):
165 # Accumulate a byte's bits, including its start position.
166 # Accumulate individual bits and their start/end sample numbers
167 # as we see them. Get the start sample number at the time when
168 # the bit value gets sampled. Assume the start of the next bit
169 # as the end sample number of the previous bit. Guess the last
170 # bit's end sample number from the second last bit's width.
171 # (gsi: Shouldn't falling SCL be the end of the bit value?)
172 # Keep the bits in receive order (MSB first) during accumulation.
173 if not self.data_bits:
174 self.ss_byte = self.samplenum
176 self.data_bits[-1][2] = self.samplenum
177 self.data_bits.append([sda, self.samplenum, self.samplenum])
178 if len(self.data_bits) < 8:
180 self.bitwidth = self.data_bits[-2][2] - self.data_bits[-3][2]
181 self.data_bits[-1][2] += self.bitwidth
183 # Get the byte value. Address and data are transmitted MSB-first.
184 d = bitpack_msb(self.data_bits, 0)
185 if self.state == 'FIND ADDRESS':
186 # The READ/WRITE bit is only in the first address byte, not
187 # in data bytes. Address bit pattern 0b1111_0xxx means that
188 # this is a 10bit slave address, another byte follows. Get
189 # the R/W direction and the address bytes count from the
190 # first byte in the I2C transfer.
192 if self.rem_addr_bytes is None:
193 if (addr_byte & 0xf8) == 0xf0:
194 self.rem_addr_bytes = 2
195 self.slave_addr_7 = None
196 self.slave_addr_10 = addr_byte & 0x06
197 self.slave_addr_10 <<= 7
199 self.rem_addr_bytes = 1
200 self.slave_addr_7 = addr_byte >> 1
201 self.slave_addr_10 = None
202 is_seven = self.slave_addr_7 is not None
203 if self.is_write is None:
204 read_bit = bool(addr_byte & 1)
205 shift_seven = self.options['address_format'] == 'shifted'
206 if is_seven and shift_seven:
208 self.is_write = False if read_bit else True
210 self.slave_addr_10 |= addr_byte
213 if self.state == 'FIND ADDRESS' and self.is_write:
214 cmd = 'ADDRESS WRITE'
216 elif self.state == 'FIND ADDRESS' and not self.is_write:
219 elif self.state == 'FIND DATA' and self.is_write:
222 elif self.state == 'FIND DATA' and not self.is_write:
226 self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth
228 # Reverse the list of bits to LSB first order before emitting
229 # annotations and passing bits to upper layers. This may be
230 # unexpected because the protocol is MSB first, but it keeps
231 # backwards compatibility.
232 self.data_bits.reverse()
233 self.putp(['BITS', self.data_bits])
236 self.putb([bin_class, bytes([d])])
238 for b, ss, es in self.data_bits:
239 cls, texts = proto['BIT'][0], proto['BIT'][1:]
240 texts = [t.format(b = b) for t in texts]
241 self.put(ss, es, self.out_ann, [cls, texts])
243 if cmd.startswith('ADDRESS') and is_seven:
244 self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
246 w = ['Write', 'Wr', 'W'] if self.is_write else ['Read', 'Rd', 'R']
248 self.ss, self.es = self.ss_byte, self.samplenum
250 cls, texts = proto[cmd][0], proto[cmd][1:]
251 texts = [t.format(b = d) for t in texts]
252 self.putx([cls, texts])
254 # Done with this packet.
255 self.data_bits.clear()
256 self.state = 'FIND ACK'
258 def get_ack(self, pins):
260 # NOTE! Re-uses the last data bit's width for ACK/NAK as well.
261 # Which might be acceptable because this decoder implementation
262 # only gets to handle ACK/NAK after all DATA BITS were seen.
263 self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
264 cmd = 'NACK' if (sda == 1) else 'ACK'
265 self.putp([cmd, None])
266 cls, texts = proto[cmd][0], proto[cmd][1:]
267 self.putx([cls, texts])
268 # Slave addresses can span one or two bytes, before data bytes
269 # follow. There can be an arbitrary number of data bytes. Stick
270 # with getting more address bytes if applicable, or enter or
271 # remain in the data phase of the transfer otherwise.
272 if self.rem_addr_bytes:
273 self.rem_addr_bytes -= 1
274 if self.rem_addr_bytes:
275 self.state = 'FIND ADDRESS'
277 self.state = 'FIND DATA'
279 def handle_stop(self, pins):
281 if self.samplerate and self.pdu_start:
282 elapsed = self.samplenum - self.pdu_start + 1
283 elapsed /= self.samplerate
284 bitrate = int(1 / elapsed * self.pdu_bits)
285 ss, es = self.pdu_start, self.samplenum
286 self.put(ss, es, self.out_bitrate, bitrate)
287 self.pdu_start = None
291 self.ss, self.es = self.samplenum, self.samplenum
292 self.putp([cmd, None])
293 cls, texts = proto[cmd][0], proto[cmd][1:]
294 self.putx([cls, texts])
295 self.state = 'FIND START'
296 self.is_repeat_start = False
298 self.data_bits.clear()
303 if self.state == 'FIND START':
304 # Wait for a START condition (S): SCL = high, SDA = falling.
305 self.handle_start(self.wait({0: 'h', 1: 'f'}))
306 elif self.state == 'FIND ADDRESS':
307 # Wait for a data bit: SCL = rising.
308 self.handle_address_or_data(self.wait({0: 'r'}))
309 elif self.state == 'FIND DATA':
310 # Wait for any of the following conditions (or combinations):
311 # a) Data sampling of receiver: SCL = rising, and/or
312 # b) START condition (S): SCL = high, SDA = falling, and/or
313 # c) STOP condition (P): SCL = high, SDA = rising
314 pins = self.wait([{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}])
316 # Check which of the condition(s) matched and handle them.
318 self.handle_address_or_data(pins)
319 elif self.matched[1]:
320 self.handle_start(pins)
321 elif self.matched[2]:
322 self.handle_stop(pins)
323 elif self.state == 'FIND ACK':
324 # Wait for a data/ack bit: SCL = rising.
325 self.get_ack(self.wait({0: 'r'}))