2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
5 ## Copyright (C) 2019 Zhiyuan Wan <dv.xw@qq.com>
6 ## Copyright (C) 2019 Kongou Hikari <hikari@iloli.bid>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
22 import sigrokdecode as srd
31 - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
32 Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
33 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
34 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
35 'EXIT2-IR', 'UPDATE-IR'.
36 - 'IR TDI': Bitstring that was clocked into the IR register.
37 - 'IR TDO': Bitstring that was clocked out of the IR register.
38 - 'DR TDI': Bitstring that was clocked into the DR register.
39 - 'DR TDO': Bitstring that was clocked out of the DR register.
41 All bitstrings are a list consisting of two items. The first is a sequence
42 of '1' and '0' characters (the right-most character is the LSB. Example:
43 '01110001', where 1 is the LSB). The second item is a list of ss/es values
44 for each bit that is in the bitstring.
49 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
51 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
52 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
54 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
55 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
59 'CJTAG-EC', 'CJTAG-SPARE', 'CJTAG-TPDEL', 'CJTAG-TPREV', 'CJTAG-TPST',
60 'CJTAG-RDYC', 'CJTAG-DLYC', 'CJTAG-SCNFMT', 'CJTAG-CP', 'CJTAG-OAC',
64 class Decoder(srd.Decoder):
68 longname = 'Compact Joint Test Action Group (IEEE 1149.7)'
69 desc = 'Protocol for testing, debugging, and flashing ICs.'
73 tags = ['Debug/trace']
75 {'id': 'tckc', 'name': 'TCKC', 'desc': 'Test clock'},
76 {'id': 'tmsc', 'name': 'TMSC', 'desc': 'Test mode select'},
79 tuple([tuple([s.lower(), s]) for s in jtag_states]) + \
80 tuple([tuple([s.lower(), s]) for s in cjtag_states]) + ( \
81 ('bit-tdi', 'Bit (TDI)'),
82 ('bit-tdo', 'Bit (TDO)'),
83 ('bitstring-tdi', 'Bitstring (TDI)'),
84 ('bitstring-tdo', 'Bitstring (TDO)'),
85 ('bit-tms', 'Bit (TMS)'),
88 ('bits-tdi', 'Bits (TDI)', (28,)),
89 ('bits-tdo', 'Bits (TDO)', (29,)),
90 ('bitstrings-tdi', 'Bitstrings (TDI)', (30,)),
91 ('bitstrings-tdo', 'Bitstrings (TDO)', (31,)),
92 ('bits-tms', 'Bits (TMS)', (32,)),
93 ('cjtag-states', 'CJTAG states',
94 tuple(range(len(jtag_states), len(jtag_states + cjtag_states)))),
95 ('jtag-states', 'JTAG states', tuple(range(len(jtag_states)))),
102 # self.state = 'TEST-LOGIC-RESET'
103 self.state = 'RUN-TEST/IDLE'
104 self.cjtagstate = '4-WIRE'
105 self.oldcjtagstate = None
106 self.escape_edges = 0
114 self.bits_samplenums_tdi = []
115 self.bits_samplenums_tdo = []
116 self.ss_item = self.es_item = None
117 self.ss_bitstring = self.es_bitstring = None
118 self.saved_item = None
120 self.first_bit = True
123 self.out_python = self.register(srd.OUTPUT_PYTHON)
124 self.out_ann = self.register(srd.OUTPUT_ANN)
126 def putx(self, data):
127 self.put(self.ss_item, self.es_item, self.out_ann, data)
129 def putp(self, data):
130 self.put(self.ss_item, self.es_item, self.out_python, data)
132 def putx_bs(self, data):
133 self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
135 def putp_bs(self, data):
136 self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
138 def advance_state_machine(self, tms):
139 self.oldstate = self.state
141 if self.cjtagstate.startswith('CJTAG-'):
143 if self.oacp > 4 and self.oaclen == 12:
144 self.cjtagstate = 'CJTAG-EC'
146 if self.oacp == 8 and tms == 0:
148 if self.oacp > 8 and self.oaclen == 36:
149 self.cjtagstate = 'CJTAG-SPARE'
150 if self.oacp > 13 and self.oaclen == 36:
151 self.cjtagstate = 'CJTAG-TPDEL'
152 if self.oacp > 16 and self.oaclen == 36:
153 self.cjtagstate = 'CJTAG-TPREV'
154 if self.oacp > 18 and self.oaclen == 36:
155 self.cjtagstate = 'CJTAG-TPST'
156 if self.oacp > 23 and self.oaclen == 36:
157 self.cjtagstate = 'CJTAG-RDYC'
158 if self.oacp > 25 and self.oaclen == 36:
159 self.cjtagstate = 'CJTAG-DLYC'
160 if self.oacp > 27 and self.oaclen == 36:
161 self.cjtagstate = 'CJTAG-SCNFMT'
163 if self.oacp > 8 and self.oaclen == 12:
164 self.cjtagstate = 'CJTAG-CP'
165 if self.oacp > 32 and self.oaclen == 36:
166 self.cjtagstate = 'CJTAG-CP'
168 if self.oacp > self.oaclen:
169 self.cjtagstate = 'OSCAN1'
171 # Because Nuclei cJTAG device asserts a reset during cJTAG
173 self.state = 'TEST-LOGIC-RESET'
177 if self.state == 'TEST-LOGIC-RESET':
178 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
179 elif self.state == 'RUN-TEST/IDLE':
180 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
183 elif self.state == 'SELECT-DR-SCAN':
184 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
185 elif self.state == 'CAPTURE-DR':
186 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
187 elif self.state == 'SHIFT-DR':
188 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
189 elif self.state == 'EXIT1-DR':
190 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
191 elif self.state == 'PAUSE-DR':
192 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
193 elif self.state == 'EXIT2-DR':
194 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
195 elif self.state == 'UPDATE-DR':
196 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
199 elif self.state == 'SELECT-IR-SCAN':
200 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
201 elif self.state == 'CAPTURE-IR':
202 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
203 elif self.state == 'SHIFT-IR':
204 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
205 elif self.state == 'EXIT1-IR':
206 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
207 elif self.state == 'PAUSE-IR':
208 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
209 elif self.state == 'EXIT2-IR':
210 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
211 elif self.state == 'UPDATE-IR':
212 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
214 def handle_rising_tckc_edge(self, tdi, tdo, tck, tms):
216 # Rising TCK edges always advance the state machine.
217 self.advance_state_machine(tms)
220 # Save the start sample and item for later (no output yet).
221 self.ss_item = self.samplenum
224 # Output the saved item (from the last CLK edge to the current).
225 self.es_item = self.samplenum
226 # Output the old state (from last rising TCK edge to current one).
227 self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
228 self.putp(['NEW STATE', self.state])
230 self.putx([len(jtag_states) + cjtag_states.index(self.oldcjtagstate),
231 [self.oldcjtagstate]])
232 if (self.oldcjtagstate.startswith('CJTAG-')):
233 self.putx([32, [str(self.oldtms)]])
236 # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values.
237 if self.oldstate.startswith('SHIFT-') or \
238 self.oldstate.startswith('EXIT1-'):
240 self.ss_bitstring = self.samplenum
241 self.first_bit = False
243 self.putx([28, [str(self.bits_tdi[0])]])
244 self.putx([29, [str(self.bits_tdo[0])]])
245 # Use self.samplenum as ES of the previous bit.
246 self.bits_samplenums_tdi[0][1] = self.samplenum
247 self.bits_samplenums_tdo[0][1] = self.samplenum
249 self.bits_tdi.insert(0, tdi)
250 self.bits_tdo.insert(0, tdo)
252 # Use self.samplenum as SS of the current bit.
253 self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
254 self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
256 # Output all TDI/TDO bits if we just switched to UPDATE-*.
257 if self.state.startswith('UPDATE-'):
259 self.es_bitstring = self.samplenum
261 t = self.state[-2:] + ' TDI'
262 b = ''.join(map(str, self.bits_tdi[1:]))
263 h = ' (0x%x' % int('0b0' + b, 2) + ')'
264 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits'
265 self.putx_bs([30, [s]])
266 self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]])
268 self.bits_samplenums_tdi = []
270 t = self.state[-2:] + ' TDO'
271 b = ''.join(map(str, self.bits_tdo[1:]))
272 h = ' (0x%x' % int('0b0' + b, 2) + ')'
273 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits'
274 self.putx_bs([31, [s]])
275 self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]])
277 self.bits_samplenums_tdo = []
279 self.first_bit = True
281 self.ss_bitstring = self.samplenum
283 self.ss_item = self.samplenum
285 def handle_tmsc_edge(self):
286 self.escape_edges += 1
288 def handle_tapc_state(self):
289 self.oldcjtagstate = self.cjtagstate
291 if self.escape_edges >= 8:
292 self.cjtagstate = '4-WIRE'
293 if self.escape_edges == 6:
294 self.cjtagstate = 'CJTAG-OAC'
298 self.escape_edges = 0
304 # Wait for a rising edge on TCKC.
305 tckc, tmsc = self.wait({0: 'r'})
306 self.handle_tapc_state()
308 if self.cjtagstate == 'OSCAN1':
309 if self.oscan1cycle == 0: # nTDI
310 tdi = 1 if (tmsc == 0) else 0
312 elif self.oscan1cycle == 1: # TMS
315 elif self.oscan1cycle == 2: # TDO
317 self.handle_rising_tckc_edge(tdi, tdo, tckc, tms)
320 self.handle_rising_tckc_edge(None, None, tckc, tmsc)
323 tckc, tmsc_n = self.wait([{0: 'f'}, {1: 'e'}])
326 self.handle_tmsc_edge()