2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
5 ## Copyright (C) 2019 Stephan Thiele <stephan.thiele@mailbox.org>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
21 from common.srdhelper import bitpack
22 import sigrokdecode as srd
24 class SamplerateError(Exception):
28 return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc]
30 class Decoder(srd.Decoder):
34 longname = 'Controller Area Network'
35 desc = 'Field bus protocol for distributed realtime control.'
41 {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
44 {'id': 'nominal_bitrate', 'desc': 'Nominal bitrate (bits/s)', 'default': 1000000},
45 {'id': 'fast_bitrate', 'desc': 'Fast bitrate (bits/s)', 'default': 2000000},
46 {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
49 ('data', 'Payload data'),
50 ('sof', 'Start of frame'),
51 ('eof', 'End of frame'),
53 ('ext-id', 'Extended identifier'),
54 ('full-id', 'Full identifier'),
55 ('ide', 'Identifier extension bit'),
56 ('reserved-bit', 'Reserved bit 0 and 1'),
57 ('rtr', 'Remote transmission request'),
58 ('srr', 'Substitute remote request'),
59 ('dlc', 'Data length count'),
60 ('crc-sequence', 'CRC sequence'),
61 ('crc-delimiter', 'CRC delimiter'),
62 ('ack-slot', 'ACK slot'),
63 ('ack-delimiter', 'ACK delimiter'),
64 ('stuff-bit', 'Stuff bit'),
65 ('warning', 'Warning'),
69 ('bits', 'Bits', (15, 17)),
70 ('fields', 'Fields', tuple(range(15))),
71 ('warnings', 'Warnings', (16,)),
78 self.samplerate = None
79 self.reset_variables()
82 self.out_ann = self.register(srd.OUTPUT_ANN)
83 self.out_python = self.register(srd.OUTPUT_PYTHON)
85 def set_bit_rate(self, bitrate):
86 self.bit_width = float(self.samplerate) / float(bitrate)
87 self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
89 def set_nominal_bitrate(self):
90 self.set_bit_rate(self.options['nominal_bitrate'])
92 def set_fast_bitrate(self):
93 self.set_bit_rate(self.options['fast_bitrate'])
95 def metadata(self, key, value):
96 if key == srd.SRD_CONF_SAMPLERATE:
97 self.samplerate = value
98 self.bit_width = float(self.samplerate) / float(self.options['nominal_bitrate'])
99 self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
101 # Generic helper for CAN bit annotations.
102 def putg(self, ss, es, data):
103 left, right = int(self.sample_point), int(self.bit_width - self.sample_point)
104 self.put(ss - left, es + right, self.out_ann, data)
106 # Single-CAN-bit annotation using the current samplenum.
107 def putx(self, data):
108 self.putg(self.samplenum, self.samplenum, data)
110 # Single-CAN-bit annotation using the samplenum of CAN bit 12.
111 def put12(self, data):
112 self.putg(self.ss_bit12, self.ss_bit12, data)
114 # Single-CAN-bit annotation using the samplenum of CAN bit 32.
115 def put32(self, data):
116 self.putg(self.ss_bit32, self.ss_bit32, data)
118 # Multi-CAN-bit annotation from self.ss_block to current samplenum.
119 def putb(self, data):
120 self.putg(self.ss_block, self.samplenum, data)
122 def putpy(self, data):
123 self.put(self.ss_packet, self.es_packet, self.out_python, data)
125 def reset_variables(self):
127 self.sof = self.frame_type = self.dlc = None
128 self.rawbits = [] # All bits, including stuff bits
129 self.bits = [] # Only actual CAN frame bits (no stuff bits)
130 self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF)
131 self.last_databit = 999 # Positive value that bitnum+x will never match
135 self.ss_databytebits = []
136 self.frame_bytes = []
141 # Poor man's clock synchronization. Use signal edges which change to
142 # dominant state in rather simple ways. This naive approach is neither
143 # aware of the SYNC phase's width nor the specific location of the edge,
144 # but improves the decoder's reliability when the input signal's bitrate
145 # does not exactly match the nominal rate.
146 def dom_edge_seen(self, force = False):
147 self.dom_edge_snum = self.samplenum
148 self.dom_edge_bcount = self.curbit
150 # Determine the position of the next desired bit's sample point.
151 def get_sample_point(self, bitnum):
152 samplenum = self.dom_edge_snum
153 samplenum += self.bit_width * (bitnum - self.dom_edge_bcount)
154 samplenum += self.sample_point
155 return int(samplenum)
157 def is_stuff_bit(self):
158 # CAN uses NRZ encoding and bit stuffing.
159 # After 5 identical bits, a stuff bit of opposite value is added.
160 # But not in the CRC delimiter, ACK, and end of frame fields.
161 if len(self.bits) > self.last_databit + 17:
163 last_6_bits = self.rawbits[-6:]
164 if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]):
167 # Stuff bit. Keep it in self.rawbits, but drop it from self.bits.
168 self.bits.pop() # Drop last bit.
171 def is_valid_crc(self, crc_bits):
174 def decode_error_frame(self, bits):
177 def decode_overload_frame(self, bits):
180 # Both standard and extended frames end with CRC, CRC delimiter, ACK,
181 # ACK delimiter, and EOF fields. Handle them in a common function.
182 # Returns True if the frame ended (EOF), False otherwise.
183 def decode_frame_end(self, can_rx, bitnum):
185 # Remember start of CRC sequence (see below).
186 if bitnum == (self.last_databit + 1):
187 self.ss_block = self.samplenum
189 if dlc2len(self.dlc) < 16:
190 self.crc_len = 27 # 17 + SBC + stuff bits
192 self.crc_len = 32 # 21 + SBC + stuff bits
196 # CRC sequence (15 bits, 17 bits or 21 bits)
197 elif bitnum == (self.last_databit + self.crc_len):
199 if dlc2len(self.dlc) < 16:
206 x = self.last_databit + 1
207 crc_bits = self.bits[x:x + self.crc_len + 1]
210 self.crc = bitpack(bits)
211 self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc),
212 '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]])
213 if not self.is_valid_crc(crc_bits):
214 self.putb([16, ['CRC is invalid']])
216 # CRC delimiter bit (recessive)
217 elif bitnum == (self.last_databit + self.crc_len + 1):
218 self.putx([12, ['CRC delimiter: %d' % can_rx,
219 'CRC d: %d' % can_rx, 'CRC d']])
221 self.putx([16, ['CRC delimiter must be a recessive bit']])
224 self.set_nominal_bitrate()
226 # ACK slot bit (dominant: ACK, recessive: NACK)
227 elif bitnum == (self.last_databit + self.crc_len + 2):
228 ack = 'ACK' if can_rx == 0 else 'NACK'
229 self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']])
231 # ACK delimiter bit (recessive)
232 elif bitnum == (self.last_databit + self.crc_len + 3):
233 self.putx([14, ['ACK delimiter: %d' % can_rx,
234 'ACK d: %d' % can_rx, 'ACK d']])
236 self.putx([16, ['ACK delimiter must be a recessive bit']])
238 # Remember start of EOF (see below).
239 elif bitnum == (self.last_databit + self.crc_len + 4):
240 self.ss_block = self.samplenum
242 # End of frame (EOF), 7 recessive bits
243 elif bitnum == (self.last_databit + self.crc_len + 10):
244 self.putb([2, ['End of frame', 'EOF', 'E']])
245 if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
246 self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
247 self.es_packet = self.samplenum
248 py_data = tuple([self.frame_type, self.fullid, self.rtr_type,
249 self.dlc, self.frame_bytes])
251 self.reset_variables()
256 # Returns True if the frame ended (EOF), False otherwise.
257 def decode_standard_frame(self, can_rx, bitnum):
259 # Bit 14: FDF (Flexible data format)
260 # Has to be sent dominant when FD frame, has to be sent recessive
261 # when classic CAN frame.
263 self.fd = True if can_rx else False
265 self.putx([7, ['Flexible data format: %d' % can_rx,
266 'FDF: %d' % can_rx, 'FDF']])
268 self.putx([7, ['Reserved bit 0: %d' % can_rx,
269 'RB0: %d' % can_rx, 'RB0']])
272 # Bit 12: Substitute remote request (SRR) bit
273 self.put12([8, ['Substitute remote request', 'SRR']])
276 # Bit 12: Remote transmission request (RTR) bit
277 # Data frame: dominant, remote frame: recessive
278 # Remote frames do not contain a data field.
279 rtr = 'remote' if self.bits[12] == 1 else 'data'
280 self.put12([8, ['Remote transmission request: %s frame' % rtr,
281 'RTR: %s frame' % rtr, 'RTR']])
285 if bitnum == 15 and self.fd:
286 self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']])
288 if bitnum == 16 and self.fd:
289 self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']])
291 if bitnum == 17 and self.fd:
292 self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']])
294 # Remember start of DLC (see below).
295 elif bitnum == self.dlc_start:
296 self.ss_block = self.samplenum
298 # Bits 15-18: Data length code (DLC), in number of bytes (0-8).
299 elif bitnum == self.dlc_start + 3:
300 bits = self.bits[self.dlc_start:self.dlc_start + 4]
302 self.dlc = bitpack(bits)
303 self.putb([10, ['Data length code: %d' % self.dlc,
304 'DLC: %d' % self.dlc, 'DLC']])
305 self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
306 if self.dlc > 8 and not self.fd:
307 self.putb([16, ['Data length code (DLC) > 8 is not allowed']])
309 # Remember all databyte bits, except the very last one.
310 elif bitnum in range(self.dlc_start + 4, self.last_databit):
311 self.ss_databytebits.append(self.samplenum)
313 # Bits 19-X: Data field (0-8 bytes, depending on DLC)
314 # The bits within a data byte are transferred MSB-first.
315 elif bitnum == self.last_databit:
316 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
317 for i in range(dlc2len(self.dlc)):
318 x = self.dlc_start + 4 + (8 * i)
319 bits = self.bits[x:x + 8]
322 self.frame_bytes.append(b)
323 ss = self.ss_databytebits[i * 8]
324 es = self.ss_databytebits[((i + 1) * 8) - 1]
325 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
326 'DB %d: 0x%02x' % (i, b), 'DB']])
327 self.ss_databytebits = []
329 elif bitnum > self.last_databit:
330 return self.decode_frame_end(can_rx, bitnum)
334 # Returns True if the frame ended (EOF), False otherwise.
335 def decode_extended_frame(self, can_rx, bitnum):
337 # Remember start of EID (see below).
339 self.ss_block = self.samplenum
343 # Bits 14-31: Extended identifier (EID[17..0])
345 bits = self.bits[14:]
347 self.eid = bitpack(bits)
348 s = '%d (0x%x)' % (self.eid, self.eid)
349 self.putb([4, ['Extended Identifier: %s' % s,
350 'Extended ID: %s' % s, 'Extended ID', 'EID']])
352 self.fullid = self.ident << 18 | self.eid
353 s = '%d (0x%x)' % (self.fullid, self.fullid)
354 self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s,
357 # Bit 12: Substitute remote request (SRR) bit
358 self.put12([9, ['Substitute remote request: %d' % self.bits[12],
359 'SRR: %d' % self.bits[12], 'SRR']])
361 # Bit 32: Remote transmission request (RTR) bit
362 # Data frame: dominant, remote frame: recessive
363 # Remote frames do not contain a data field.
365 # Remember start of RTR (see below).
367 self.ss_bit32 = self.samplenum
371 rtr = 'remote' if can_rx == 1 else 'data'
372 self.putx([8, ['Remote transmission request: %s frame' % rtr,
373 'RTR: %s frame' % rtr, 'RTR']])
376 # Bit 33: RB1 (reserved bit)
378 self.fd = True if can_rx else False
381 self.putx([7, ['Flexible data format: %d' % can_rx,
382 'FDF: %d' % can_rx, 'FDF']])
383 self.put32([7, ['Reserved bit 1: %d' % self.rtr,
384 'RB1: %d' % self.rtr, 'RB1']])
386 self.putx([7, ['Reserved bit 1: %d' % can_rx,
387 'RB1: %d' % can_rx, 'RB1']])
389 # Bit 34: RB0 (reserved bit)
391 self.putx([7, ['Reserved bit 0: %d' % can_rx,
392 'RB0: %d' % can_rx, 'RB0']])
394 elif bitnum == 35 and self.fd:
395 self.putx([7, ['Bit rate switch: %d' % can_rx,
396 'BRS: %d' % can_rx, 'BRS']])
398 elif bitnum == 36 and self.fd:
399 self.putx([7, ['Error state indicator: %d' % can_rx,
400 'ESI: %d' % can_rx, 'ESI']])
402 # Remember start of DLC (see below).
403 elif bitnum == self.dlc_start:
404 self.ss_block = self.samplenum
406 # Bits 35-38: Data length code (DLC), in number of bytes (0-8).
407 elif bitnum == self.dlc_start + 3:
408 bits = self.bits[self.dlc_start:self.dlc_start + 4]
410 self.dlc = bitpack(bits)
411 self.putb([10, ['Data length code: %d' % self.dlc,
412 'DLC: %d' % self.dlc, 'DLC']])
413 self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
415 # Remember all databyte bits, except the very last one.
416 elif bitnum in range(self.dlc_start + 4, self.last_databit):
417 self.ss_databytebits.append(self.samplenum)
419 # Bits 39-X: Data field (0-8 bytes, depending on DLC)
420 # The bits within a data byte are transferred MSB-first.
421 elif bitnum == self.last_databit:
422 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
423 for i in range(dlc2len(self.dlc)):
424 x = self.dlc_start + 4 + (8 * i)
425 bits = self.bits[x:x + 8]
428 self.frame_bytes.append(b)
429 ss = self.ss_databytebits[i * 8]
430 es = self.ss_databytebits[((i + 1) * 8) - 1]
431 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
432 'DB %d: 0x%02x' % (i, b), 'DB']])
433 self.ss_databytebits = []
435 elif bitnum > self.last_databit:
436 return self.decode_frame_end(can_rx, bitnum)
440 def handle_bit(self, can_rx):
441 self.rawbits.append(can_rx)
442 self.bits.append(can_rx)
444 # Get the index of the current CAN frame bit (without stuff bits).
445 bitnum = len(self.bits) - 1
447 if self.fd and can_rx:
448 if bitnum == 16 and self.frame_type == 'standard' \
449 or bitnum == 35 and self.frame_type == 'extended':
450 self.dom_edge_seen(force=True)
451 self.set_fast_bitrate()
453 # If this is a stuff bit, remove it from self.bits and ignore it.
454 if self.is_stuff_bit():
455 self.putx([15, [str(can_rx)]])
456 self.curbit += 1 # Increase self.curbit (bitnum is not affected).
459 self.putx([17, [str(can_rx)]])
461 # Bit 0: Start of frame (SOF) bit
463 self.ss_packet = self.samplenum
464 self.putx([1, ['Start of frame', 'SOF', 'S']])
466 self.putx([16, ['Start of frame (SOF) must be a dominant bit']])
468 # Remember start of ID (see below).
470 self.ss_block = self.samplenum
472 # Bits 1-11: Identifier (ID[10..0])
473 # The bits ID[10..4] must NOT be all recessive.
477 # BEWARE! Don't clobber the decoder's .id field which is
478 # part of its boiler plate!
479 self.ident = bitpack(bits)
480 self.fullid = self.ident
481 s = '%d (0x%x)' % (self.ident, self.ident),
482 self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
483 if (self.ident & 0x7f0) == 0x7f0:
484 self.putb([16, ['Identifier bits 10..4 must not be all recessive']])
486 # RTR or SRR bit, depending on frame type (gets handled later).
488 # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only.
489 self.ss_bit12 = self.samplenum
491 # Bit 13: Identifier extension (IDE) bit
492 # Standard frame: dominant, extended frame: recessive
494 ide = self.frame_type = 'standard' if can_rx == 0 else 'extended'
495 self.putx([6, ['Identifier extension bit: %s frame' % ide,
496 'IDE: %s frame' % ide, 'IDE']])
498 # Bits 14-X: Frame-type dependent, passed to the resp. handlers.
500 if self.frame_type == 'standard':
501 done = self.decode_standard_frame(can_rx, bitnum)
503 done = self.decode_extended_frame(can_rx, bitnum)
505 # The handlers return True if a frame ended (EOF).
509 # After a frame there are 3 intermission bits (recessive).
510 # After these bits, the bus is considered free.
515 if not self.samplerate:
516 raise SamplerateError('Cannot decode without samplerate.')
520 if self.state == 'IDLE':
521 # Wait for a dominant state (logic 0) on the bus.
522 (can_rx,) = self.wait({0: 'l'})
523 self.sof = self.samplenum
524 self.dom_edge_seen(force = True)
525 self.state = 'GET BITS'
526 elif self.state == 'GET BITS':
527 # Wait until we're in the correct bit/sampling position.
528 pos = self.get_sample_point(self.curbit)
529 (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}])
533 self.handle_bit(can_rx)