2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
22 class SamplerateError(Exception):
25 class Decoder(srd.Decoder):
29 longname = 'Controller Area Network'
30 desc = 'Field bus protocol for distributed realtime control.'
35 {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
38 {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000},
39 {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
42 ('data', 'CAN payload data'),
43 ('sof', 'Start of frame'),
44 ('eof', 'End of frame'),
46 ('ext-id', 'Extended identifier'),
47 ('full-id', 'Full identifier'),
48 ('ide', 'Identifier extension bit'),
49 ('reserved-bit', 'Reserved bit 0 and 1'),
50 ('rtr', 'Remote transmission request'),
51 ('srr', 'Substitute remote request'),
52 ('dlc', 'Data length count'),
53 ('crc-sequence', 'CRC sequence'),
54 ('crc-delimiter', 'CRC delimiter'),
55 ('ack-slot', 'ACK slot'),
56 ('ack-delimiter', 'ACK delimiter'),
57 ('stuff-bit', 'Stuff bit'),
58 ('warnings', 'Human-readable warnings'),
62 ('bits', 'Bits', (15, 17)),
63 ('fields', 'Fields', tuple(range(15))),
64 ('warnings', 'Warnings', (16,)),
68 self.samplerate = None
69 self.reset_variables()
72 self.out_ann = self.register(srd.OUTPUT_ANN)
74 def metadata(self, key, value):
75 if key == srd.SRD_CONF_SAMPLERATE:
76 self.samplerate = value
77 self.bit_width = float(self.samplerate) / float(self.options['bitrate'])
78 self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
80 # Generic helper for CAN bit annotations.
81 def putg(self, ss, es, data):
82 left, right = int(self.sample_point), int(self.bit_width - self.sample_point)
83 self.put(ss - left, es + right, self.out_ann, data)
85 # Single-CAN-bit annotation using the current samplenum.
87 self.putg(self.samplenum, self.samplenum, data)
89 # Single-CAN-bit annotation using the samplenum of CAN bit 12.
90 def put12(self, data):
91 self.putg(self.ss_bit12, self.ss_bit12, data)
93 # Multi-CAN-bit annotation from self.ss_block to current samplenum.
95 self.putg(self.ss_block, self.samplenum, data)
97 def reset_variables(self):
99 self.sof = self.frame_type = self.dlc = None
100 self.rawbits = [] # All bits, including stuff bits
101 self.bits = [] # Only actual CAN frame bits (no stuff bits)
102 self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF)
103 self.last_databit = 999 # Positive value that bitnum+x will never match
106 self.ss_databytebits = []
108 # Poor man's clock synchronization. Use signal edges which change to
109 # dominant state in rather simple ways. This naive approach is neither
110 # aware of the SYNC phase's width nor the specific location of the edge,
111 # but improves the decoder's reliability when the input signal's bitrate
112 # does not exactly match the nominal rate.
113 def dom_edge_seen(self, force = False):
114 self.dom_edge_snum = self.samplenum
115 self.dom_edge_bcount = self.curbit
117 def bit_sampled(self):
121 # Determine the position of the next desired bit's sample point.
122 def get_sample_point(self, bitnum):
123 samplenum = self.dom_edge_snum
124 samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount))
125 samplenum += int(self.sample_point)
128 def is_stuff_bit(self):
129 # CAN uses NRZ encoding and bit stuffing.
130 # After 5 identical bits, a stuff bit of opposite value is added.
131 # But not in the CRC delimiter, ACK, and end of frame fields.
132 if len(self.bits) > self.last_databit + 16:
134 last_6_bits = self.rawbits[-6:]
135 if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]):
138 # Stuff bit. Keep it in self.rawbits, but drop it from self.bits.
139 self.bits.pop() # Drop last bit.
142 def is_valid_crc(self, crc_bits):
145 def decode_error_frame(self, bits):
148 def decode_overload_frame(self, bits):
151 # Both standard and extended frames end with CRC, CRC delimiter, ACK,
152 # ACK delimiter, and EOF fields. Handle them in a common function.
153 # Returns True if the frame ended (EOF), False otherwise.
154 def decode_frame_end(self, can_rx, bitnum):
156 # Remember start of CRC sequence (see below).
157 if bitnum == (self.last_databit + 1):
158 self.ss_block = self.samplenum
160 # CRC sequence (15 bits)
161 elif bitnum == (self.last_databit + 15):
162 x = self.last_databit + 1
163 crc_bits = self.bits[x:x + 15 + 1]
164 self.crc = int(''.join(str(d) for d in crc_bits), 2)
165 self.putb([11, ['CRC sequence: 0x%04x' % self.crc,
166 'CRC: 0x%04x' % self.crc, 'CRC']])
167 if not self.is_valid_crc(crc_bits):
168 self.putb([16, ['CRC is invalid']])
170 # CRC delimiter bit (recessive)
171 elif bitnum == (self.last_databit + 16):
172 self.putx([12, ['CRC delimiter: %d' % can_rx,
173 'CRC d: %d' % can_rx, 'CRC d']])
175 self.putx([16, ['CRC delimiter must be a recessive bit']])
177 # ACK slot bit (dominant: ACK, recessive: NACK)
178 elif bitnum == (self.last_databit + 17):
179 ack = 'ACK' if can_rx == 0 else 'NACK'
180 self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']])
182 # ACK delimiter bit (recessive)
183 elif bitnum == (self.last_databit + 18):
184 self.putx([14, ['ACK delimiter: %d' % can_rx,
185 'ACK d: %d' % can_rx, 'ACK d']])
187 self.putx([16, ['ACK delimiter must be a recessive bit']])
189 # Remember start of EOF (see below).
190 elif bitnum == (self.last_databit + 19):
191 self.ss_block = self.samplenum
193 # End of frame (EOF), 7 recessive bits
194 elif bitnum == (self.last_databit + 25):
195 self.putb([2, ['End of frame', 'EOF', 'E']])
196 if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
197 self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
198 self.reset_variables()
203 # Returns True if the frame ended (EOF), False otherwise.
204 def decode_standard_frame(self, can_rx, bitnum):
206 # Bit 14: RB0 (reserved bit)
207 # Has to be sent dominant, but receivers should accept recessive too.
209 self.putx([7, ['Reserved bit 0: %d' % can_rx,
210 'RB0: %d' % can_rx, 'RB0']])
212 # Bit 12: Remote transmission request (RTR) bit
213 # Data frame: dominant, remote frame: recessive
214 # Remote frames do not contain a data field.
215 rtr = 'remote' if self.bits[12] == 1 else 'data'
216 self.put12([8, ['Remote transmission request: %s frame' % rtr,
217 'RTR: %s frame' % rtr, 'RTR']])
219 # Remember start of DLC (see below).
221 self.ss_block = self.samplenum
223 # Bits 15-18: Data length code (DLC), in number of bytes (0-8).
225 self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2)
226 self.putb([10, ['Data length code: %d' % self.dlc,
227 'DLC: %d' % self.dlc, 'DLC']])
228 self.last_databit = 18 + (self.dlc * 8)
230 self.putb([16, ['Data length code (DLC) > 8 is not allowed']])
232 # Remember all databyte bits, except the very last one.
233 elif bitnum in range(19, self.last_databit):
234 self.ss_databytebits.append(self.samplenum)
236 # Bits 19-X: Data field (0-8 bytes, depending on DLC)
237 # The bits within a data byte are transferred MSB-first.
238 elif bitnum == self.last_databit:
239 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
240 for i in range(self.dlc):
242 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
243 ss = self.ss_databytebits[i * 8]
244 es = self.ss_databytebits[((i + 1) * 8) - 1]
245 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
246 'DB %d: 0x%02x' % (i, b), 'DB']])
247 self.ss_databytebits = []
249 elif bitnum > self.last_databit:
250 return self.decode_frame_end(can_rx, bitnum)
254 # Returns True if the frame ended (EOF), False otherwise.
255 def decode_extended_frame(self, can_rx, bitnum):
257 # Remember start of EID (see below).
259 self.ss_block = self.samplenum
261 # Bits 14-31: Extended identifier (EID[17..0])
263 self.eid = int(''.join(str(d) for d in self.bits[14:]), 2)
264 s = '%d (0x%x)' % (self.eid, self.eid)
265 self.putb([4, ['Extended Identifier: %s' % s,
266 'Extended ID: %s' % s, 'Extended ID', 'EID']])
268 self.fullid = self.id << 18 | self.eid
269 s = '%d (0x%x)' % (self.fullid, self.fullid)
270 self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s,
273 # Bit 12: Substitute remote request (SRR) bit
274 self.put12([9, ['Substitute remote request: %d' % self.bits[12],
275 'SRR: %d' % self.bits[12], 'SRR']])
277 # Bit 32: Remote transmission request (RTR) bit
278 # Data frame: dominant, remote frame: recessive
279 # Remote frames do not contain a data field.
281 rtr = 'remote' if can_rx == 1 else 'data'
282 self.putx([8, ['Remote transmission request: %s frame' % rtr,
283 'RTR: %s frame' % rtr, 'RTR']])
285 # Bit 33: RB1 (reserved bit)
287 self.putx([7, ['Reserved bit 1: %d' % can_rx,
288 'RB1: %d' % can_rx, 'RB1']])
290 # Bit 34: RB0 (reserved bit)
292 self.putx([7, ['Reserved bit 0: %d' % can_rx,
293 'RB0: %d' % can_rx, 'RB0']])
295 # Remember start of DLC (see below).
297 self.ss_block = self.samplenum
299 # Bits 35-38: Data length code (DLC), in number of bytes (0-8).
301 self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2)
302 self.putb([10, ['Data length code: %d' % self.dlc,
303 'DLC: %d' % self.dlc, 'DLC']])
304 self.last_databit = 38 + (self.dlc * 8)
306 # Remember all databyte bits, except the very last one.
307 elif bitnum in range(39, self.last_databit):
308 self.ss_databytebits.append(self.samplenum)
310 # Bits 39-X: Data field (0-8 bytes, depending on DLC)
311 # The bits within a data byte are transferred MSB-first.
312 elif bitnum == self.last_databit:
313 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
314 for i in range(self.dlc):
316 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
317 ss = self.ss_databytebits[i * 8]
318 es = self.ss_databytebits[((i + 1) * 8) - 1]
319 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
320 'DB %d: 0x%02x' % (i, b), 'DB']])
321 self.ss_databytebits = []
323 elif bitnum > self.last_databit:
324 return self.decode_frame_end(can_rx, bitnum)
328 def handle_bit(self, can_rx):
329 self.rawbits.append(can_rx)
330 self.bits.append(can_rx)
332 # Get the index of the current CAN frame bit (without stuff bits).
333 bitnum = len(self.bits) - 1
335 # If this is a stuff bit, remove it from self.bits and ignore it.
336 if self.is_stuff_bit():
337 self.putx([15, [str(can_rx)]])
338 self.curbit += 1 # Increase self.curbit (bitnum is not affected).
341 self.putx([17, [str(can_rx)]])
343 # Bit 0: Start of frame (SOF) bit
345 self.putx([1, ['Start of frame', 'SOF', 'S']])
347 self.putx([16, ['Start of frame (SOF) must be a dominant bit']])
349 # Remember start of ID (see below).
351 self.ss_block = self.samplenum
353 # Bits 1-11: Identifier (ID[10..0])
354 # The bits ID[10..4] must NOT be all recessive.
356 self.id = int(''.join(str(d) for d in self.bits[1:]), 2)
357 s = '%d (0x%x)' % (self.id, self.id),
358 self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
359 if (self.id & 0x7f0) == 0x7f0:
360 self.putb([16, ['Identifier bits 10..4 must not be all recessive']])
362 # RTR or SRR bit, depending on frame type (gets handled later).
364 # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only.
365 self.ss_bit12 = self.samplenum
367 # Bit 13: Identifier extension (IDE) bit
368 # Standard frame: dominant, extended frame: recessive
370 ide = self.frame_type = 'standard' if can_rx == 0 else 'extended'
371 self.putx([6, ['Identifier extension bit: %s frame' % ide,
372 'IDE: %s frame' % ide, 'IDE']])
374 # Bits 14-X: Frame-type dependent, passed to the resp. handlers.
376 if self.frame_type == 'standard':
377 done = self.decode_standard_frame(can_rx, bitnum)
379 done = self.decode_extended_frame(can_rx, bitnum)
381 # The handlers return True if a frame ended (EOF).
385 # After a frame there are 3 intermission bits (recessive).
386 # After these bits, the bus is considered free.
391 if not self.samplerate:
392 raise SamplerateError('Cannot decode without samplerate.')
396 if self.state == 'IDLE':
397 # Wait for a dominant state (logic 0) on the bus.
398 (can_rx,) = self.wait({0: 'l'})
399 self.sof = self.samplenum
400 self.dom_edge_seen(force = True)
401 self.state = 'GET BITS'
402 elif self.state == 'GET BITS':
403 # Wait until we're in the correct bit/sampling position.
404 pos = self.get_sample_point(self.curbit)
405 (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}])
409 self.handle_bit(can_rx)