2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
5 ## Copyright (C) 2019 Stephan Thiele <stephan.thiele@mailbox.org>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
21 import sigrokdecode as srd
23 class SamplerateError(Exception):
27 return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc]
29 class Decoder(srd.Decoder):
33 longname = 'Controller Area Network'
34 desc = 'Field bus protocol for distributed realtime control.'
40 {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
43 {'id': 'nominal_bitrate', 'desc': 'Nominal bitrate (bits/s)', 'default': 1000000},
44 {'id': 'fast_bitrate', 'desc': 'Fast bitrate (bits/s)', 'default': 2000000},
45 {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
48 ('data', 'CAN payload data'),
49 ('sof', 'Start of frame'),
50 ('eof', 'End of frame'),
52 ('ext-id', 'Extended identifier'),
53 ('full-id', 'Full identifier'),
54 ('ide', 'Identifier extension bit'),
55 ('reserved-bit', 'Reserved bit 0 and 1'),
56 ('rtr', 'Remote transmission request'),
57 ('srr', 'Substitute remote request'),
58 ('dlc', 'Data length count'),
59 ('crc-sequence', 'CRC sequence'),
60 ('crc-delimiter', 'CRC delimiter'),
61 ('ack-slot', 'ACK slot'),
62 ('ack-delimiter', 'ACK delimiter'),
63 ('stuff-bit', 'Stuff bit'),
64 ('warnings', 'Human-readable warnings'),
68 ('bits', 'Bits', (15, 17)),
69 ('fields', 'Fields', tuple(range(15))),
70 ('warnings', 'Warnings', (16,)),
77 self.samplerate = None
78 self.reset_variables()
81 self.out_ann = self.register(srd.OUTPUT_ANN)
83 def set_bit_rate(self, bitrate):
84 self.bit_width = float(self.samplerate) / float(bitrate)
85 self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
87 def set_nominal_bitrate(self):
88 self.set_bit_rate(self.options['nominal_bitrate'])
90 def set_fast_bitrate(self):
91 self.set_bit_rate(self.options['fast_bitrate'])
93 def metadata(self, key, value):
94 if key == srd.SRD_CONF_SAMPLERATE:
95 self.samplerate = value
96 self.bit_width = float(self.samplerate) / float(self.options['nominal_bitrate'])
97 self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
99 # Generic helper for CAN bit annotations.
100 def putg(self, ss, es, data):
101 left, right = int(self.sample_point), int(self.bit_width - self.sample_point)
102 self.put(ss - left, es + right, self.out_ann, data)
104 # Single-CAN-bit annotation using the current samplenum.
105 def putx(self, data):
106 self.putg(self.samplenum, self.samplenum, data)
108 # Single-CAN-bit annotation using the samplenum of CAN bit 12.
109 def put12(self, data):
110 self.putg(self.ss_bit12, self.ss_bit12, data)
112 # Single-CAN-bit annotation using the samplenum of CAN bit 32.
113 def put32(self, data):
114 self.putg(self.ss_bit32, self.ss_bit32, data)
116 # Multi-CAN-bit annotation from self.ss_block to current samplenum.
117 def putb(self, data):
118 self.putg(self.ss_block, self.samplenum, data)
120 def reset_variables(self):
122 self.sof = self.frame_type = self.dlc = None
123 self.rawbits = [] # All bits, including stuff bits
124 self.bits = [] # Only actual CAN frame bits (no stuff bits)
125 self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF)
126 self.last_databit = 999 # Positive value that bitnum+x will never match
130 self.ss_databytebits = []
134 # Poor man's clock synchronization. Use signal edges which change to
135 # dominant state in rather simple ways. This naive approach is neither
136 # aware of the SYNC phase's width nor the specific location of the edge,
137 # but improves the decoder's reliability when the input signal's bitrate
138 # does not exactly match the nominal rate.
139 def dom_edge_seen(self, force = False):
140 self.dom_edge_snum = self.samplenum
141 self.dom_edge_bcount = self.curbit
143 def bit_sampled(self):
147 # Determine the position of the next desired bit's sample point.
148 def get_sample_point(self, bitnum):
149 samplenum = self.dom_edge_snum
150 samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount))
151 samplenum += int(self.sample_point)
154 def is_stuff_bit(self):
155 # CAN uses NRZ encoding and bit stuffing.
156 # After 5 identical bits, a stuff bit of opposite value is added.
157 # But not in the CRC delimiter, ACK, and end of frame fields.
158 if len(self.bits) > self.last_databit + 17:
160 last_6_bits = self.rawbits[-6:]
161 if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]):
164 # Stuff bit. Keep it in self.rawbits, but drop it from self.bits.
165 self.bits.pop() # Drop last bit.
168 def is_valid_crc(self, crc_bits):
171 def decode_error_frame(self, bits):
174 def decode_overload_frame(self, bits):
177 # Both standard and extended frames end with CRC, CRC delimiter, ACK,
178 # ACK delimiter, and EOF fields. Handle them in a common function.
179 # Returns True if the frame ended (EOF), False otherwise.
180 def decode_frame_end(self, can_rx, bitnum):
182 # Remember start of CRC sequence (see below).
183 if bitnum == (self.last_databit + 1):
184 self.ss_block = self.samplenum
186 if dlc2len(self.dlc) < 16:
187 self.crc_len = 27 # 17 + SBC + stuff bits
189 self.crc_len = 32 # 21 + SBC + stuff bits
193 # CRC sequence (15 bits, 17 bits or 21 bits)
194 elif bitnum == (self.last_databit + self.crc_len):
196 if dlc2len(self.dlc) < 16:
203 x = self.last_databit + 1
204 crc_bits = self.bits[x:x + self.crc_len + 1]
205 self.crc = int(''.join(str(d) for d in crc_bits), 2)
206 self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc),
207 '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]])
208 if not self.is_valid_crc(crc_bits):
209 self.putb([16, ['CRC is invalid']])
211 # CRC delimiter bit (recessive)
212 elif bitnum == (self.last_databit + self.crc_len + 1):
213 self.putx([12, ['CRC delimiter: %d' % can_rx,
214 'CRC d: %d' % can_rx, 'CRC d']])
216 self.putx([16, ['CRC delimiter must be a recessive bit']])
219 self.set_nominal_bitrate()
221 # ACK slot bit (dominant: ACK, recessive: NACK)
222 elif bitnum == (self.last_databit + self.crc_len + 2):
223 ack = 'ACK' if can_rx == 0 else 'NACK'
224 self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']])
226 # ACK delimiter bit (recessive)
227 elif bitnum == (self.last_databit + self.crc_len + 3):
228 self.putx([14, ['ACK delimiter: %d' % can_rx,
229 'ACK d: %d' % can_rx, 'ACK d']])
231 self.putx([16, ['ACK delimiter must be a recessive bit']])
233 # Remember start of EOF (see below).
234 elif bitnum == (self.last_databit + self.crc_len + 4):
235 self.ss_block = self.samplenum
237 # End of frame (EOF), 7 recessive bits
238 elif bitnum == (self.last_databit + self.crc_len + 10):
239 self.putb([2, ['End of frame', 'EOF', 'E']])
240 if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
241 self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
242 self.reset_variables()
247 # Returns True if the frame ended (EOF), False otherwise.
248 def decode_standard_frame(self, can_rx, bitnum):
250 # Bit 14: FDF (Flexible data format)
251 # Has to be sent dominant when FD frame, has to be sent recessive
252 # when classic CAN frame.
254 self.fd = True if can_rx else False
256 self.putx([7, ['Flexible data format: %d' % can_rx,
257 'FDF: %d' % can_rx, 'FDF']])
259 self.putx([7, ['Reserved bit 0: %d' % can_rx,
260 'RB0: %d' % can_rx, 'RB0']])
263 # Bit 12: Substitute remote request (SRR) bit
264 self.put12([8, ['Substitute remote request', 'SRR']])
267 # Bit 12: Remote transmission request (RTR) bit
268 # Data frame: dominant, remote frame: recessive
269 # Remote frames do not contain a data field.
270 rtr = 'remote' if self.bits[12] == 1 else 'data'
271 self.put12([8, ['Remote transmission request: %s frame' % rtr,
272 'RTR: %s frame' % rtr, 'RTR']])
275 if bitnum == 15 and self.fd:
276 self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']])
278 if bitnum == 16 and self.fd:
279 self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']])
281 if bitnum == 17 and self.fd:
282 self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']])
284 # Remember start of DLC (see below).
285 elif bitnum == self.dlc_start:
286 self.ss_block = self.samplenum
288 # Bits 15-18: Data length code (DLC), in number of bytes (0-8).
289 elif bitnum == self.dlc_start + 3:
290 self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2)
291 self.putb([10, ['Data length code: %d' % self.dlc,
292 'DLC: %d' % self.dlc, 'DLC']])
293 self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
294 if self.dlc > 8 and not self.fd:
295 self.putb([16, ['Data length code (DLC) > 8 is not allowed']])
297 # Remember all databyte bits, except the very last one.
298 elif bitnum in range(self.dlc_start + 4, self.last_databit):
299 self.ss_databytebits.append(self.samplenum)
301 # Bits 19-X: Data field (0-8 bytes, depending on DLC)
302 # The bits within a data byte are transferred MSB-first.
303 elif bitnum == self.last_databit:
304 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
305 for i in range(dlc2len(self.dlc)):
306 x = self.dlc_start + 4 + (8 * i)
307 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
308 ss = self.ss_databytebits[i * 8]
309 es = self.ss_databytebits[((i + 1) * 8) - 1]
310 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
311 'DB %d: 0x%02x' % (i, b), 'DB']])
312 self.ss_databytebits = []
314 elif bitnum > self.last_databit:
315 return self.decode_frame_end(can_rx, bitnum)
319 # Returns True if the frame ended (EOF), False otherwise.
320 def decode_extended_frame(self, can_rx, bitnum):
322 # Remember start of EID (see below).
324 self.ss_block = self.samplenum
328 # Bits 14-31: Extended identifier (EID[17..0])
330 self.eid = int(''.join(str(d) for d in self.bits[14:]), 2)
331 s = '%d (0x%x)' % (self.eid, self.eid)
332 self.putb([4, ['Extended Identifier: %s' % s,
333 'Extended ID: %s' % s, 'Extended ID', 'EID']])
335 self.fullid = self.id << 18 | self.eid
336 s = '%d (0x%x)' % (self.fullid, self.fullid)
337 self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s,
340 # Bit 12: Substitute remote request (SRR) bit
341 self.put12([9, ['Substitute remote request: %d' % self.bits[12],
342 'SRR: %d' % self.bits[12], 'SRR']])
344 # Bit 32: Remote transmission request (RTR) bit
345 # Data frame: dominant, remote frame: recessive
346 # Remote frames do not contain a data field.
348 # Remember start of RTR (see below).
350 self.ss_bit32 = self.samplenum
354 rtr = 'remote' if can_rx == 1 else 'data'
355 self.putx([8, ['Remote transmission request: %s frame' % rtr,
356 'RTR: %s frame' % rtr, 'RTR']])
358 # Bit 33: RB1 (reserved bit)
360 self.fd = True if can_rx else False
363 self.putx([7, ['Flexible data format: %d' % can_rx,
364 'FDF: %d' % can_rx, 'FDF']])
365 self.put32([7, ['Reserved bit 1: %d' % self.rtr,
366 'RB1: %d' % self.rtr, 'RB1']])
368 self.putx([7, ['Reserved bit 1: %d' % can_rx,
369 'RB1: %d' % can_rx, 'RB1']])
371 # Bit 34: RB0 (reserved bit)
373 self.putx([7, ['Reserved bit 0: %d' % can_rx,
374 'RB0: %d' % can_rx, 'RB0']])
376 elif bitnum == 35 and self.fd:
377 self.putx([7, ['Bit rate switch: %d' % can_rx,
378 'BRS: %d' % can_rx, 'BRS']])
380 elif bitnum == 36 and self.fd:
381 self.putx([7, ['Error state indicator: %d' % can_rx,
382 'ESI: %d' % can_rx, 'ESI']])
384 # Remember start of DLC (see below).
385 elif bitnum == self.dlc_start:
386 self.ss_block = self.samplenum
388 # Bits 35-38: Data length code (DLC), in number of bytes (0-8).
389 elif bitnum == self.dlc_start + 3:
390 self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2)
391 self.putb([10, ['Data length code: %d' % self.dlc,
392 'DLC: %d' % self.dlc, 'DLC']])
393 self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
395 # Remember all databyte bits, except the very last one.
396 elif bitnum in range(self.dlc_start + 4, self.last_databit):
397 self.ss_databytebits.append(self.samplenum)
399 # Bits 39-X: Data field (0-8 bytes, depending on DLC)
400 # The bits within a data byte are transferred MSB-first.
401 elif bitnum == self.last_databit:
402 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
403 for i in range(dlc2len(self.dlc)):
404 x = self.dlc_start + 4 + (8 * i)
405 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
406 ss = self.ss_databytebits[i * 8]
407 es = self.ss_databytebits[((i + 1) * 8) - 1]
408 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
409 'DB %d: 0x%02x' % (i, b), 'DB']])
410 self.ss_databytebits = []
412 elif bitnum > self.last_databit:
413 return self.decode_frame_end(can_rx, bitnum)
417 def handle_bit(self, can_rx):
418 self.rawbits.append(can_rx)
419 self.bits.append(can_rx)
421 # Get the index of the current CAN frame bit (without stuff bits).
422 bitnum = len(self.bits) - 1
424 if self.fd and can_rx:
425 if bitnum == 16 and self.frame_type == 'standard' \
426 or bitnum == 35 and self.frame_type == 'extended':
427 self.dom_edge_seen(force=True)
428 self.set_fast_bitrate()
430 # If this is a stuff bit, remove it from self.bits and ignore it.
431 if self.is_stuff_bit():
432 self.putx([15, [str(can_rx)]])
433 self.curbit += 1 # Increase self.curbit (bitnum is not affected).
436 self.putx([17, [str(can_rx)]])
438 # Bit 0: Start of frame (SOF) bit
440 self.putx([1, ['Start of frame', 'SOF', 'S']])
442 self.putx([16, ['Start of frame (SOF) must be a dominant bit']])
444 # Remember start of ID (see below).
446 self.ss_block = self.samplenum
448 # Bits 1-11: Identifier (ID[10..0])
449 # The bits ID[10..4] must NOT be all recessive.
451 self.id = int(''.join(str(d) for d in self.bits[1:]), 2)
452 s = '%d (0x%x)' % (self.id, self.id),
453 self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
454 if (self.id & 0x7f0) == 0x7f0:
455 self.putb([16, ['Identifier bits 10..4 must not be all recessive']])
457 # RTR or SRR bit, depending on frame type (gets handled later).
459 # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only.
460 self.ss_bit12 = self.samplenum
462 # Bit 13: Identifier extension (IDE) bit
463 # Standard frame: dominant, extended frame: recessive
465 ide = self.frame_type = 'standard' if can_rx == 0 else 'extended'
466 self.putx([6, ['Identifier extension bit: %s frame' % ide,
467 'IDE: %s frame' % ide, 'IDE']])
469 # Bits 14-X: Frame-type dependent, passed to the resp. handlers.
471 if self.frame_type == 'standard':
472 done = self.decode_standard_frame(can_rx, bitnum)
474 done = self.decode_extended_frame(can_rx, bitnum)
476 # The handlers return True if a frame ended (EOF).
480 # After a frame there are 3 intermission bits (recessive).
481 # After these bits, the bus is considered free.
486 if not self.samplerate:
487 raise SamplerateError('Cannot decode without samplerate.')
491 if self.state == 'IDLE':
492 # Wait for a dominant state (logic 0) on the bus.
493 (can_rx,) = self.wait({0: 'l'})
494 self.sof = self.samplenum
495 self.dom_edge_seen(force = True)
496 self.state = 'GET BITS'
497 elif self.state == 'GET BITS':
498 # Wait until we're in the correct bit/sampling position.
499 pos = self.get_sample_point(self.curbit)
500 (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}])
504 self.handle_bit(can_rx)