[libsigrokdecode.git] / decoders / usb_signalling / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# USB signalling (low-speed and full-speed) protocol decoder

import sigrokdecode as srd

'''
Protocol output format:

Packet:
[<ptype>, <pdata>]

<ptype>, <pdata>:
 - 'SOP', None
 - 'SYM', <sym>
 - 'BIT', <bit>
 - 'STUFF BIT', None
 - 'EOP', None

<sym>:
 - 'J', 'K', 'SE0', or 'SE1'

<bit>:
 - 0 or 1
 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
'''

# Low-/full-speed symbols.
# Note: Low-speed J and K are inverted compared to the full-speed J and K!
symbols = {
    'low-speed': {
        # (<dp>, <dm>): <symbol/state>
        (0, 0): 'SE0',
        (1, 0): 'K',
        (0, 1): 'J',
        (1, 1): 'SE1',
    },
    'full-speed': {
        # (<dp>, <dm>): <symbol/state>
        (0, 0): 'SE0',
        (1, 0): 'J',
        (0, 1): 'K',
        (1, 1): 'SE1',
    },
}

bitrates = {
    'low-speed': 1500000,   # 1.5Mb/s (+/- 1.5%)
    'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'usb_signalling'
    name = 'USB signalling'
    longname = 'Universal Serial Bus (LS/FS) signalling'
    desc = 'USB (low-speed and full-speed) signalling protocol.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['usb_signalling']
    probes = [
        {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
        {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
    ]
    optional_probes = []
    options = {
        'signalling': ['Signalling', 'full-speed'],
    }
    annotations = [
        ['sym', 'Symbol'],
        ['sop', 'Start of packet (SOP)'],
        ['eop', 'End of packet (EOP)'],
        ['bit', 'Bit'],
        ['stuffbit', 'Stuff bit'],
    ]

    def __init__(self):
        self.oldsym = 'J' # The "idle" state is J.
        self.ss_sop = None
        self.ss_block = None
        self.samplenum = 0
        self.syms = []
        self.bitrate = None
        self.bitwidth = None
        self.bitnum = 0
        self.samplenum_target = None
        self.oldpins = None
        self.consecutive_ones = 0
        self.state = 'IDLE'

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
        self.bitrate = bitrates[self.options['signalling']]
        self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
        self.halfbit = int(self.bitwidth / 2)

    def report(self):
        pass

    def putpx(self, data):
        self.put(self.samplenum, self.samplenum, self.out_proto, data)

    def putx(self, data):
        self.put(self.samplenum, self.samplenum, self.out_ann, data)

    def putpm(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(self.ss_block - h, s + h, self.out_proto, data)

    def putm(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(self.ss_block - h, s + h, self.out_ann, data)

    def putpb(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(s - h, s + h, self.out_proto, data)

    def putb(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(s - h, s + h, self.out_ann, data)

    def set_new_target_samplenum(self):
        bitpos = self.ss_sop + (self.bitwidth / 2)
        bitpos += self.bitnum * self.bitwidth
        self.samplenum_target = int(bitpos)

    def wait_for_sop(self, sym):
        # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
        if sym != 'K':
            self.oldsym = sym
            return
        self.ss_sop = self.samplenum
        self.set_new_target_samplenum()
        self.putpx(['SOP', None])
        self.putx([1, ['SOP']])
        self.state = 'GET BIT'

    def handle_bit(self, sym, b):
        if self.consecutive_ones == 6 and b == '0':
            # Stuff bit.
            self.putpb(['STUFF BIT', None])
            self.putb([4, ['SB: %s/%s' % (sym, b)]])
            self.consecutive_ones = 0
        else:
            # Normal bit (not a stuff bit).
            self.putpb(['BIT', b])
            self.putb([3, ['%s/%s' % (sym, b)]])
            if b == '1':
                self.consecutive_ones += 1
            else:
                self.consecutive_ones = 0

    def get_eop(self, sym):
        # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
        self.syms.append(sym)
        self.putpb(['SYM', sym])
        self.putb([0, ['%s' % sym]])
        self.bitnum += 1
        self.set_new_target_samplenum()
        self.oldsym = sym
        if self.syms[-2:] == ['SE0', 'J']:
            # Got an EOP.
            self.putpm(['EOP', None])
            self.putm([2, ['EOP']])
            self.bitnum, self.syms, self.state = 0, [], 'IDLE'
            self.consecutive_ones = 0

    def get_bit(self, sym):
        if sym == 'SE0':
            # Start of an EOP. Change state, run get_eop() for this bit.
            self.state = 'GET EOP'
            self.ss_block = self.samplenum
            self.get_eop(sym)
            return
        self.syms.append(sym)
        self.putpb(['SYM', sym])
        b = '0' if self.oldsym != sym else '1'
        self.handle_bit(sym, b)
        self.bitnum += 1
        self.set_new_target_samplenum()
        self.oldsym = sym

    def decode(self, ss, es, data):
        for (self.samplenum, pins) in data:
            # State machine.
            if self.state == 'IDLE':
                # Ignore identical samples early on (for performance reasons).
                if self.oldpins == pins:
                    continue
                self.oldpins = pins
                sym = symbols[self.options['signalling']][tuple(pins)]
                self.wait_for_sop(sym)
            elif self.state in ('GET BIT', 'GET EOP'):
                # Wait until we're in the middle of the desired bit.
                if self.samplenum < self.samplenum_target:
                    continue
                sym = symbols[self.options['signalling']][tuple(pins)]
                if self.state == 'GET BIT':
                    self.get_bit(sym)
                elif self.state == 'GET EOP':
                    self.get_eop(sym)
            else:
                raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	# USB signalling (low-speed and full-speed) protocol decoder
	23
	24	import sigrokdecode as srd
	25
	26	'''
	27	Protocol output format:
	28
	29	Packet:
	30	[<ptype>, <pdata>]
	31
	32	<ptype>, <pdata>:
	33	- 'SOP', None
	34	- 'SYM', <sym>
	35	- 'BIT', <bit>
	36	- 'STUFF BIT', None
	37	- 'EOP', None
	38
	39	<sym>:
	40	- 'J', 'K', 'SE0', or 'SE1'
	41
	42	<bit>:
	43	- 0 or 1
	44	- Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
	45	'''
	46
	47	# Low-/full-speed symbols.
	48	# Note: Low-speed J and K are inverted compared to the full-speed J and K!
	49	symbols = {
	50	'low-speed': {
	51	# (<dp>, <dm>): <symbol/state>
	52	(0, 0): 'SE0',
	53	(1, 0): 'K',
	54	(0, 1): 'J',
	55	(1, 1): 'SE1',
	56	},
	57	'full-speed': {
	58	# (<dp>, <dm>): <symbol/state>
	59	(0, 0): 'SE0',
	60	(1, 0): 'J',
	61	(0, 1): 'K',
	62	(1, 1): 'SE1',
	63	},
	64	}
	65
	66	bitrates = {
	67	'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
	68	'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
	69	}
	70
	71	class Decoder(srd.Decoder):
	72	api_version = 1
	73	id = 'usb_signalling'
	74	name = 'USB signalling'
	75	longname = 'Universal Serial Bus (LS/FS) signalling'
	76	desc = 'USB (low-speed and full-speed) signalling protocol.'
	77	license = 'gplv2+'
	78	inputs = ['logic']
	79	outputs = ['usb_signalling']
	80	probes = [
	81	{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
	82	{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
	83	]
	84	optional_probes = []
	85	options = {
	86	'signalling': ['Signalling', 'full-speed'],
	87	}
	88	annotations = [
	89	['sym', 'Symbol'],
	90	['sop', 'Start of packet (SOP)'],
	91	['eop', 'End of packet (EOP)'],
	92	['bit', 'Bit'],
	93	['stuffbit', 'Stuff bit'],
	94	]
	95
	96	def __init__(self):
	97	self.oldsym = 'J' # The "idle" state is J.
	98	self.ss_sop = None
	99	self.ss_block = None
	100	self.samplenum = 0
	101	self.syms = []
	102	self.bitrate = None
	103	self.bitwidth = None
	104	self.bitnum = 0
	105	self.samplenum_target = None
	106	self.oldpins = None
	107	self.consecutive_ones = 0
	108	self.state = 'IDLE'
	109
	110	def start(self, metadata):
	111	self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling')
	112	self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
	113	self.bitrate = bitrates[self.options['signalling']]
	114	self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
	115	self.halfbit = int(self.bitwidth / 2)
	116
	117	def report(self):
	118	pass
	119
	120	def putpx(self, data):
	121	self.put(self.samplenum, self.samplenum, self.out_proto, data)
	122
	123	def putx(self, data):
	124	self.put(self.samplenum, self.samplenum, self.out_ann, data)
	125
	126	def putpm(self, data):
	127	s, h = self.samplenum, self.halfbit
	128	self.put(self.ss_block - h, s + h, self.out_proto, data)
	129
	130	def putm(self, data):
	131	s, h = self.samplenum, self.halfbit
	132	self.put(self.ss_block - h, s + h, self.out_ann, data)
	133
	134	def putpb(self, data):
	135	s, h = self.samplenum, self.halfbit
	136	self.put(s - h, s + h, self.out_proto, data)
	137
	138	def putb(self, data):
	139	s, h = self.samplenum, self.halfbit
	140	self.put(s - h, s + h, self.out_ann, data)
	141
	142	def set_new_target_samplenum(self):
	143	bitpos = self.ss_sop + (self.bitwidth / 2)
	144	bitpos += self.bitnum * self.bitwidth
	145	self.samplenum_target = int(bitpos)
	146
	147	def wait_for_sop(self, sym):
	148	# Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
	149	if sym != 'K':
	150	self.oldsym = sym
	151	return
	152	self.ss_sop = self.samplenum
	153	self.set_new_target_samplenum()
	154	self.putpx(['SOP', None])
	155	self.putx([1, ['SOP']])
	156	self.state = 'GET BIT'
	157
	158	def handle_bit(self, sym, b):
	159	if self.consecutive_ones == 6 and b == '0':
	160	# Stuff bit.
	161	self.putpb(['STUFF BIT', None])
	162	self.putb([4, ['SB: %s/%s' % (sym, b)]])
	163	self.consecutive_ones = 0
	164	else:
	165	# Normal bit (not a stuff bit).
	166	self.putpb(['BIT', b])
	167	self.putb([3, ['%s/%s' % (sym, b)]])
	168	if b == '1':
	169	self.consecutive_ones += 1
	170	else:
	171	self.consecutive_ones = 0
	172
	173	def get_eop(self, sym):
	174	# EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
	175	self.syms.append(sym)
	176	self.putpb(['SYM', sym])
	177	self.putb([0, ['%s' % sym]])
	178	self.bitnum += 1
	179	self.set_new_target_samplenum()
	180	self.oldsym = sym
	181	if self.syms[-2:] == ['SE0', 'J']:
	182	# Got an EOP.
	183	self.putpm(['EOP', None])
	184	self.putm([2, ['EOP']])
	185	self.bitnum, self.syms, self.state = 0, [], 'IDLE'
	186	self.consecutive_ones = 0
	187
	188	def get_bit(self, sym):
	189	if sym == 'SE0':
	190	# Start of an EOP. Change state, run get_eop() for this bit.
	191	self.state = 'GET EOP'
	192	self.ss_block = self.samplenum
	193	self.get_eop(sym)
	194	return
	195	self.syms.append(sym)
	196	self.putpb(['SYM', sym])
	197	b = '0' if self.oldsym != sym else '1'
	198	self.handle_bit(sym, b)
	199	self.bitnum += 1
	200	self.set_new_target_samplenum()
	201	self.oldsym = sym
	202
	203	def decode(self, ss, es, data):
	204	for (self.samplenum, pins) in data:
	205	# State machine.
	206	if self.state == 'IDLE':
	207	# Ignore identical samples early on (for performance reasons).
	208	if self.oldpins == pins:
	209	continue
	210	self.oldpins = pins
	211	sym = symbols[self.options['signalling']][tuple(pins)]
	212	self.wait_for_sop(sym)
	213	elif self.state in ('GET BIT', 'GET EOP'):
	214	# Wait until we're in the middle of the desired bit.
	215	if self.samplenum < self.samplenum_target:
	216	continue
	217	sym = symbols[self.options['signalling']][tuple(pins)]
	218	if self.state == 'GET BIT':
	219	self.get_bit(sym)
	220	elif self.state == 'GET EOP':
	221	self.get_eop(sym)
	222	else:
	223	raise Exception('Invalid state: %s' % self.state)
	224