[libsigrokdecode.git] / decoders / uart / uart.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# UART protocol decoder

import sigrokdecode as srd

# Used for differentiating between the two data directions.
RX = 0
TX = 1

# Annotation feed formats
ANN_ASCII = 0
ANN_DEC = 1
ANN_HEX = 2
ANN_OCT = 3
ANN_BITS = 4

# Given a parity type to check (odd, even, zero, one), the value of the
# parity bit, the value of the data, and the length of the data (5-9 bits,
# usually 8 bits) return True if the parity is correct, False otherwise.
# 'none' is _not_ allowed as value for 'parity_type'.
def parity_ok(parity_type, parity_bit, data, num_data_bits):

    # Handle easy cases first (parity bit is always 1 or 0).
    if parity_type == 'zero':
        return parity_bit == 0
    elif parity_type == 'one':
        return parity_bit == 1

    # Count number of 1 (high) bits in the data (and the parity bit itself!).
    ones = bin(data).count('1') + parity_bit

    # Check for odd/even parity.
    if parity_type == 'odd':
        return (ones % 2) == 1
    elif parity_type == 'even':
        return (ones % 2) == 0
    else:
        raise Exception('Invalid parity type: %d' % parity_type)

class Decoder(srd.Decoder):
    api_version = 1
    id = 'uart'
    name = 'UART'
    longname = 'Universal Asynchronous Receiver/Transmitter'
    desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['uart']
    probes = [
        # Allow specifying only one of the signals, e.g. if only one data
        # direction exists (or is relevant).
        {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
        {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
    ]
    optional_probes = []
    options = {
        'baudrate': ['Baud rate', 115200],
        'num_data_bits': ['Data bits', 8], # Valid: 5-9.
        'parity_type': ['Parity type', 'none'],
        'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
        'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
        'bit_order': ['Bit order', 'lsb-first'],
        # TODO: Options to invert the signal(s).
    }
    annotations = [
        ['ASCII', 'Data bytes as ASCII characters'],
        ['Decimal', 'Databytes as decimal, integer values'],
        ['Hex', 'Data bytes in hex format'],
        ['Octal', 'Data bytes as octal numbers'],
        ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
    ]

    def putx(self, rxtx, data):
        self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data)

    def __init__(self, **kwargs):
        self.samplenum = 0
        self.frame_start = [-1, -1]
        self.startbit = [-1, -1]
        self.cur_data_bit = [0, 0]
        self.databyte = [0, 0]
        self.paritybit = [-1, -1]
        self.stopbit1 = [-1, -1]
        self.startsample = [-1, -1]
        self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
        self.oldbit = [None, None]

    def start(self, metadata):
        self.samplerate = metadata['samplerate']
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')

        # The width of one UART bit in number of samples.
        self.bit_width = \
            float(self.samplerate) / float(self.options['baudrate'])

    def report(self):
        pass

    # Return true if we reached the middle of the desired bit, false otherwise.
    def reached_bit(self, rxtx, bitnum):
        # bitpos is the samplenumber which is in the middle of the
        # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
        # (if used) or the first stop bit, and so on).
        bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
        bitpos += bitnum * self.bit_width
        if self.samplenum >= bitpos:
            return True
        return False

    def reached_bit_last(self, rxtx, bitnum):
        bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width)
        if self.samplenum >= bitpos:
            return True
        return False

    def wait_for_start_bit(self, rxtx, old_signal, signal):
        # The start bit is always 0 (low). As the idle UART (and the stop bit)
        # level is 1 (high), the beginning of a start bit is a falling edge.
        if not (old_signal == 1 and signal == 0):
            return

        # Save the sample number where the start bit begins.
        self.frame_start[rxtx] = self.samplenum

        self.state[rxtx] = 'GET START BIT'

    def get_start_bit(self, rxtx, signal):
        # Skip samples until we're in the middle of the start bit.
        if not self.reached_bit(rxtx, 0):
            return

        self.startbit[rxtx] = signal

        # The startbit must be 0. If not, we report an error.
        if self.startbit[rxtx] != 0:
            self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
                     ['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
            # TODO: Abort? Ignore rest of the frame?

        self.cur_data_bit[rxtx] = 0
        self.databyte[rxtx] = 0
        self.startsample[rxtx] = -1

        self.state[rxtx] = 'GET DATA BITS'

        self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
                 ['STARTBIT', rxtx, self.startbit[rxtx]])
        self.put(self.frame_start[rxtx], self.samplenum, self.out_ann,
                 [ANN_ASCII, ['Start bit', 'Start', 'S']])

    def get_data_bits(self, rxtx, signal):
        # Skip samples until we're in the middle of the desired data bit.
        if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
            return

        # Save the sample number where the data byte starts.
        if self.startsample[rxtx] == -1:
            self.startsample[rxtx] = self.samplenum

        # Get the next data bit in LSB-first or MSB-first fashion.
        if self.options['bit_order'] == 'lsb-first':
            self.databyte[rxtx] >>= 1
            self.databyte[rxtx] |= \
                (signal << (self.options['num_data_bits'] - 1))
        elif self.options['bit_order'] == 'msb-first':
            self.databyte[rxtx] <<= 1
            self.databyte[rxtx] |= (signal << 0)
        else:
            raise Exception('Invalid bit order value: %s',
                            self.options['bit_order'])

        # Return here, unless we already received all data bits.
        # TODO? Off-by-one?
        if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
            self.cur_data_bit[rxtx] += 1
            return

        self.state[rxtx] = 'GET PARITY BIT'

        self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto,
                 ['DATA', rxtx, self.databyte[rxtx]])

        s = 'RX: ' if (rxtx == RX) else 'TX: '
        self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]])
        self.putx(rxtx, [ANN_DEC,   [s + str(self.databyte[rxtx])]])
        self.putx(rxtx, [ANN_HEX,   [s + hex(self.databyte[rxtx]),
                                     s + hex(self.databyte[rxtx])[2:]]])
        self.putx(rxtx, [ANN_OCT,   [s + oct(self.databyte[rxtx]),
                                     s + oct(self.databyte[rxtx])[2:]]])
        self.putx(rxtx, [ANN_BITS,  [s + bin(self.databyte[rxtx]),
                                     s + bin(self.databyte[rxtx])[2:]]])

    def get_parity_bit(self, rxtx, signal):
        # If no parity is used/configured, skip to the next state immediately.
        if self.options['parity_type'] == 'none':
            self.state[rxtx] = 'GET STOP BITS'
            return

        # Skip samples until we're in the middle of the parity bit.
        if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1):
            return

        self.paritybit[rxtx] = signal

        self.state[rxtx] = 'GET STOP BITS'

        if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
                     self.databyte[rxtx], self.options['num_data_bits']):
            # TODO: Fix range.
            self.put(self.samplenum, self.samplenum, self.out_proto,
                     ['PARITYBIT', rxtx, self.paritybit[rxtx]])
            self.put(self.samplenum, self.samplenum, self.out_ann,
                     [ANN_ASCII, ['Parity bit', 'Parity', 'P']])
        else:
            # TODO: Fix range.
            # TODO: Return expected/actual parity values.
            self.put(self.samplenum, self.samplenum, self.out_proto,
                     ['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
            self.put(self.samplenum, self.samplenum, self.out_ann,
                     [ANN_ASCII, ['Parity error', 'Parity err', 'PE']])

    # TODO: Currently only supports 1 stop bit.
    def get_stop_bits(self, rxtx, signal):
        # Skip samples until we're in the middle of the stop bit(s).
        skip_parity = 0 if self.options['parity_type'] == 'none' else 1
        b = self.options['num_data_bits'] + 1 + skip_parity
        if not self.reached_bit(rxtx, b):
            return

        self.stopbit1[rxtx] = signal

        # Stop bits must be 1. If not, we report an error.
        if self.stopbit1[rxtx] != 1:
            self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
                     ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
            # TODO: Abort? Ignore the frame? Other?

        self.state[rxtx] = 'WAIT FOR START BIT'

        # TODO: Fix range.
        self.put(self.samplenum, self.samplenum, self.out_proto,
                 ['STOPBIT', rxtx, self.stopbit1[rxtx]])
        self.put(self.samplenum, self.samplenum, self.out_ann,
                 [ANN_ASCII, ['Stop bit', 'Stop', 'P']])

    def decode(self, ss, es, data):
        # TODO: Either RX or TX could be omitted (optional probe).
        for (self.samplenum, (rx, tx)) in data:

            # First sample: Save RX/TX value.
            if self.oldbit[RX] == None:
                self.oldbit[RX] = rx
                continue
            if self.oldbit[TX] == None:
                self.oldbit[TX] = tx
                continue

            # State machine.
            for rxtx in (RX, TX):
                signal = rx if (rxtx == RX) else tx

                if self.state[rxtx] == 'WAIT FOR START BIT':
                    self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
                elif self.state[rxtx] == 'GET START BIT':
                    self.get_start_bit(rxtx, signal)
                elif self.state[rxtx] == 'GET DATA BITS':
                    self.get_data_bits(rxtx, signal)
                elif self.state[rxtx] == 'GET PARITY BIT':
                    self.get_parity_bit(rxtx, signal)
                elif self.state[rxtx] == 'GET STOP BITS':
                    self.get_stop_bits(rxtx, signal)
                else:
                    raise Exception('Invalid state: %d' % self.state[rxtx])

                # Save current RX/TX values for the next round.
                self.oldbit[rxtx] = signal
Commit	Line	Data
	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# UART protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	# Used for differentiating between the two data directions.
	26	RX = 0
	27	TX = 1
	28
	29	# Annotation feed formats
	30	ANN_ASCII = 0
	31	ANN_DEC = 1
	32	ANN_HEX = 2
	33	ANN_OCT = 3
	34	ANN_BITS = 4
	35
	36	# Given a parity type to check (odd, even, zero, one), the value of the
	37	# parity bit, the value of the data, and the length of the data (5-9 bits,
	38	# usually 8 bits) return True if the parity is correct, False otherwise.
	39	# 'none' is _not_ allowed as value for 'parity_type'.
	40	def parity_ok(parity_type, parity_bit, data, num_data_bits):
	41
	42	# Handle easy cases first (parity bit is always 1 or 0).
	43	if parity_type == 'zero':
	44	return parity_bit == 0
	45	elif parity_type == 'one':
	46	return parity_bit == 1
	47
	48	# Count number of 1 (high) bits in the data (and the parity bit itself!).
	49	ones = bin(data).count('1') + parity_bit
	50
	51	# Check for odd/even parity.
	52	if parity_type == 'odd':
	53	return (ones % 2) == 1
	54	elif parity_type == 'even':
	55	return (ones % 2) == 0
	56	else:
	57	raise Exception('Invalid parity type: %d' % parity_type)
	58
	59	class Decoder(srd.Decoder):
	60	api_version = 1
	61	id = 'uart'
	62	name = 'UART'
	63	longname = 'Universal Asynchronous Receiver/Transmitter'
	64	desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
	65	license = 'gplv2+'
	66	inputs = ['logic']
	67	outputs = ['uart']
	68	probes = [
	69	# Allow specifying only one of the signals, e.g. if only one data
	70	# direction exists (or is relevant).
	71	{'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
	72	{'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
	73	]
	74	optional_probes = []
	75	options = {
	76	'baudrate': ['Baud rate', 115200],
	77	'num_data_bits': ['Data bits', 8], # Valid: 5-9.
	78	'parity_type': ['Parity type', 'none'],
	79	'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
	80	'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
	81	'bit_order': ['Bit order', 'lsb-first'],
	82	# TODO: Options to invert the signal(s).
	83	}
	84	annotations = [
	85	['ASCII', 'Data bytes as ASCII characters'],
	86	['Decimal', 'Databytes as decimal, integer values'],
	87	['Hex', 'Data bytes in hex format'],
	88	['Octal', 'Data bytes as octal numbers'],
	89	['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
	90	]
	91
	92	def putx(self, rxtx, data):
	93	self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data)
	94
	95	def __init__(self, **kwargs):
	96	self.samplenum = 0
	97	self.frame_start = [-1, -1]
	98	self.startbit = [-1, -1]
	99	self.cur_data_bit = [0, 0]
	100	self.databyte = [0, 0]
	101	self.paritybit = [-1, -1]
	102	self.stopbit1 = [-1, -1]
	103	self.startsample = [-1, -1]
	104	self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
	105	self.oldbit = [None, None]
	106
	107	def start(self, metadata):
	108	self.samplerate = metadata['samplerate']
	109	self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
	110	self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
	111
	112	# The width of one UART bit in number of samples.
	113	self.bit_width = \
	114	float(self.samplerate) / float(self.options['baudrate'])
	115
	116	def report(self):
	117	pass
	118
	119	# Return true if we reached the middle of the desired bit, false otherwise.
	120	def reached_bit(self, rxtx, bitnum):
	121	# bitpos is the samplenumber which is in the middle of the
	122	# specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
	123	# (if used) or the first stop bit, and so on).
	124	bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
	125	bitpos += bitnum * self.bit_width
	126	if self.samplenum >= bitpos:
	127	return True
	128	return False
	129
	130	def reached_bit_last(self, rxtx, bitnum):
	131	bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width)
	132	if self.samplenum >= bitpos:
	133	return True
	134	return False
	135
	136	def wait_for_start_bit(self, rxtx, old_signal, signal):
	137	# The start bit is always 0 (low). As the idle UART (and the stop bit)
	138	# level is 1 (high), the beginning of a start bit is a falling edge.
	139	if not (old_signal == 1 and signal == 0):
	140	return
	141
	142	# Save the sample number where the start bit begins.
	143	self.frame_start[rxtx] = self.samplenum
	144
	145	self.state[rxtx] = 'GET START BIT'
	146
	147	def get_start_bit(self, rxtx, signal):
	148	# Skip samples until we're in the middle of the start bit.
	149	if not self.reached_bit(rxtx, 0):
	150	return
	151
	152	self.startbit[rxtx] = signal
	153
	154	# The startbit must be 0. If not, we report an error.
	155	if self.startbit[rxtx] != 0:
	156	self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
	157	['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
	158	# TODO: Abort? Ignore rest of the frame?
	159
	160	self.cur_data_bit[rxtx] = 0
	161	self.databyte[rxtx] = 0
	162	self.startsample[rxtx] = -1
	163
	164	self.state[rxtx] = 'GET DATA BITS'
	165
	166	self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
	167	['STARTBIT', rxtx, self.startbit[rxtx]])
	168	self.put(self.frame_start[rxtx], self.samplenum, self.out_ann,
	169	[ANN_ASCII, ['Start bit', 'Start', 'S']])
	170
	171	def get_data_bits(self, rxtx, signal):
	172	# Skip samples until we're in the middle of the desired data bit.
	173	if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
	174	return
	175
	176	# Save the sample number where the data byte starts.
	177	if self.startsample[rxtx] == -1:
	178	self.startsample[rxtx] = self.samplenum
	179
	180	# Get the next data bit in LSB-first or MSB-first fashion.
	181	if self.options['bit_order'] == 'lsb-first':
	182	self.databyte[rxtx] >>= 1
	183	self.databyte[rxtx] \|= \
	184	(signal << (self.options['num_data_bits'] - 1))
	185	elif self.options['bit_order'] == 'msb-first':
	186	self.databyte[rxtx] <<= 1
	187	self.databyte[rxtx] \|= (signal << 0)
	188	else:
	189	raise Exception('Invalid bit order value: %s',
	190	self.options['bit_order'])
	191
	192	# Return here, unless we already received all data bits.
	193	# TODO? Off-by-one?
	194	if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
	195	self.cur_data_bit[rxtx] += 1
	196	return
	197
	198	self.state[rxtx] = 'GET PARITY BIT'
	199
	200	self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto,
	201	['DATA', rxtx, self.databyte[rxtx]])
	202
	203	s = 'RX: ' if (rxtx == RX) else 'TX: '
	204	self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]])
	205	self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]])
	206	self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]),
	207	s + hex(self.databyte[rxtx])[2:]]])
	208	self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]),
	209	s + oct(self.databyte[rxtx])[2:]]])
	210	self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]),
	211	s + bin(self.databyte[rxtx])[2:]]])
	212
	213	def get_parity_bit(self, rxtx, signal):
	214	# If no parity is used/configured, skip to the next state immediately.
	215	if self.options['parity_type'] == 'none':
	216	self.state[rxtx] = 'GET STOP BITS'
	217	return
	218
	219	# Skip samples until we're in the middle of the parity bit.
	220	if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1):
	221	return
	222
	223	self.paritybit[rxtx] = signal
	224
	225	self.state[rxtx] = 'GET STOP BITS'
	226
	227	if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
	228	self.databyte[rxtx], self.options['num_data_bits']):
	229	# TODO: Fix range.
	230	self.put(self.samplenum, self.samplenum, self.out_proto,
	231	['PARITYBIT', rxtx, self.paritybit[rxtx]])
	232	self.put(self.samplenum, self.samplenum, self.out_ann,
	233	[ANN_ASCII, ['Parity bit', 'Parity', 'P']])
	234	else:
	235	# TODO: Fix range.
	236	# TODO: Return expected/actual parity values.
	237	self.put(self.samplenum, self.samplenum, self.out_proto,
	238	['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
	239	self.put(self.samplenum, self.samplenum, self.out_ann,
	240	[ANN_ASCII, ['Parity error', 'Parity err', 'PE']])
	241
	242	# TODO: Currently only supports 1 stop bit.
	243	def get_stop_bits(self, rxtx, signal):
	244	# Skip samples until we're in the middle of the stop bit(s).
	245	skip_parity = 0 if self.options['parity_type'] == 'none' else 1
	246	b = self.options['num_data_bits'] + 1 + skip_parity
	247	if not self.reached_bit(rxtx, b):
	248	return
	249
	250	self.stopbit1[rxtx] = signal
	251
	252	# Stop bits must be 1. If not, we report an error.
	253	if self.stopbit1[rxtx] != 1:
	254	self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
	255	['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
	256	# TODO: Abort? Ignore the frame? Other?
	257
	258	self.state[rxtx] = 'WAIT FOR START BIT'
	259
	260	# TODO: Fix range.
	261	self.put(self.samplenum, self.samplenum, self.out_proto,
	262	['STOPBIT', rxtx, self.stopbit1[rxtx]])
	263	self.put(self.samplenum, self.samplenum, self.out_ann,
	264	[ANN_ASCII, ['Stop bit', 'Stop', 'P']])
	265
	266	def decode(self, ss, es, data):
	267	# TODO: Either RX or TX could be omitted (optional probe).
	268	for (self.samplenum, (rx, tx)) in data:
	269
	270	# First sample: Save RX/TX value.
	271	if self.oldbit[RX] == None:
	272	self.oldbit[RX] = rx
	273	continue
	274	if self.oldbit[TX] == None:
	275	self.oldbit[TX] = tx
	276	continue
	277
	278	# State machine.
	279	for rxtx in (RX, TX):
	280	signal = rx if (rxtx == RX) else tx
	281
	282	if self.state[rxtx] == 'WAIT FOR START BIT':
	283	self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
	284	elif self.state[rxtx] == 'GET START BIT':
	285	self.get_start_bit(rxtx, signal)
	286	elif self.state[rxtx] == 'GET DATA BITS':
	287	self.get_data_bits(rxtx, signal)
	288	elif self.state[rxtx] == 'GET PARITY BIT':
	289	self.get_parity_bit(rxtx, signal)
	290	elif self.state[rxtx] == 'GET STOP BITS':
	291	self.get_stop_bits(rxtx, signal)
	292	else:
	293	raise Exception('Invalid state: %d' % self.state[rxtx])
	294
	295	# Save current RX/TX values for the next round.
	296	self.oldbit[rxtx] = signal
	297