]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | ''' | |
24 | OUTPUT_PYTHON format: | |
25 | ||
26 | UART packet: | |
27 | [<packet-type>, <rxtx>, <packet-data>] | |
28 | ||
29 | This is the list of <packet-type>s and their respective <packet-data>: | |
30 | - 'STARTBIT': The data is the (integer) value of the start bit (0/1). | |
31 | - 'DATA': The data is the (integer) value of the UART data. Valid values | |
32 | range from 0 to 512 (as the data can be up to 9 bits in size). | |
33 | - 'DATABITS': List of data bits and their ss/es numbers. | |
34 | - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1). | |
35 | - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). | |
36 | - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1). | |
37 | - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1). | |
38 | - 'PARITY ERROR': The data is a tuple with two entries. The first one is | |
39 | the expected parity value, the second is the actual parity value. | |
40 | - TODO: Frame error? | |
41 | ||
42 | The <rxtx> field is 0 for RX packets, 1 for TX packets. | |
43 | ''' | |
44 | ||
45 | # Used for differentiating between the two data directions. | |
46 | RX = 0 | |
47 | TX = 1 | |
48 | ||
49 | # Given a parity type to check (odd, even, zero, one), the value of the | |
50 | # parity bit, the value of the data, and the length of the data (5-9 bits, | |
51 | # usually 8 bits) return True if the parity is correct, False otherwise. | |
52 | # 'none' is _not_ allowed as value for 'parity_type'. | |
53 | def parity_ok(parity_type, parity_bit, data, num_data_bits): | |
54 | ||
55 | # Handle easy cases first (parity bit is always 1 or 0). | |
56 | if parity_type == 'zero': | |
57 | return parity_bit == 0 | |
58 | elif parity_type == 'one': | |
59 | return parity_bit == 1 | |
60 | ||
61 | # Count number of 1 (high) bits in the data (and the parity bit itself!). | |
62 | ones = bin(data).count('1') + parity_bit | |
63 | ||
64 | # Check for odd/even parity. | |
65 | if parity_type == 'odd': | |
66 | return (ones % 2) == 1 | |
67 | elif parity_type == 'even': | |
68 | return (ones % 2) == 0 | |
69 | else: | |
70 | raise Exception('Invalid parity type: %d' % parity_type) | |
71 | ||
72 | class Decoder(srd.Decoder): | |
73 | api_version = 1 | |
74 | id = 'uart' | |
75 | name = 'UART' | |
76 | longname = 'Universal Asynchronous Receiver/Transmitter' | |
77 | desc = 'Asynchronous, serial bus.' | |
78 | license = 'gplv2+' | |
79 | inputs = ['logic'] | |
80 | outputs = ['uart'] | |
81 | optional_channels = ( | |
82 | # Allow specifying only one of the signals, e.g. if only one data | |
83 | # direction exists (or is relevant). | |
84 | {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, | |
85 | {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, | |
86 | ) | |
87 | options = ( | |
88 | {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200}, | |
89 | {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8, | |
90 | 'values': (5, 6, 7, 8, 9)}, | |
91 | {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none', | |
92 | 'values': ('none', 'odd', 'even', 'zero', 'one')}, | |
93 | {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes', | |
94 | 'values': ('yes', 'no')}, | |
95 | {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0, | |
96 | 'values': (0.0, 0.5, 1.0, 1.5)}, | |
97 | {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first', | |
98 | 'values': ('lsb-first', 'msb-first')}, | |
99 | {'id': 'format', 'desc': 'Data format', 'default': 'ascii', | |
100 | 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, | |
101 | # TODO: Options to invert the signal(s). | |
102 | ) | |
103 | annotations = ( | |
104 | ('rx-data', 'RX data'), | |
105 | ('tx-data', 'TX data'), | |
106 | ('rx-start', 'RX start bits'), | |
107 | ('tx-start', 'TX start bits'), | |
108 | ('rx-parity-ok', 'RX parity OK bits'), | |
109 | ('tx-parity-ok', 'TX parity OK bits'), | |
110 | ('rx-parity-err', 'RX parity error bits'), | |
111 | ('tx-parity-err', 'TX parity error bits'), | |
112 | ('rx-stop', 'RX stop bits'), | |
113 | ('tx-stop', 'TX stop bits'), | |
114 | ('rx-warnings', 'RX warnings'), | |
115 | ('tx-warnings', 'TX warnings'), | |
116 | ('rx-data-bits', 'RX data bits'), | |
117 | ('tx-data-bits', 'TX data bits'), | |
118 | ) | |
119 | annotation_rows = ( | |
120 | ('rx-data', 'RX', (0, 2, 4, 6, 8)), | |
121 | ('rx-data-bits', 'RX bits', (12,)), | |
122 | ('rx-warnings', 'RX warnings', (10,)), | |
123 | ('tx-data', 'TX', (1, 3, 5, 7, 9)), | |
124 | ('tx-data-bits', 'TX bits', (13,)), | |
125 | ('tx-warnings', 'TX warnings', (11,)), | |
126 | ) | |
127 | binary = ( | |
128 | ('rx', 'RX dump'), | |
129 | ('tx', 'TX dump'), | |
130 | ('rxtx', 'RX/TX dump'), | |
131 | ) | |
132 | ||
133 | def putx(self, rxtx, data): | |
134 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) | |
135 | self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data) | |
136 | ||
137 | def putpx(self, rxtx, data): | |
138 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) | |
139 | self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data) | |
140 | ||
141 | def putg(self, data): | |
142 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
143 | self.put(s - halfbit, s + halfbit, self.out_ann, data) | |
144 | ||
145 | def putp(self, data): | |
146 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
147 | self.put(s - halfbit, s + halfbit, self.out_python, data) | |
148 | ||
149 | def putbin(self, rxtx, data): | |
150 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) | |
151 | self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data) | |
152 | ||
153 | def __init__(self, **kwargs): | |
154 | self.samplerate = None | |
155 | self.samplenum = 0 | |
156 | self.frame_start = [-1, -1] | |
157 | self.startbit = [-1, -1] | |
158 | self.cur_data_bit = [0, 0] | |
159 | self.databyte = [0, 0] | |
160 | self.paritybit = [-1, -1] | |
161 | self.stopbit1 = [-1, -1] | |
162 | self.startsample = [-1, -1] | |
163 | self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] | |
164 | self.oldbit = [1, 1] | |
165 | self.oldpins = [1, 1] | |
166 | self.databits = [[], []] | |
167 | ||
168 | def start(self): | |
169 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
170 | self.out_bin = self.register(srd.OUTPUT_BINARY) | |
171 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
172 | ||
173 | def metadata(self, key, value): | |
174 | if key == srd.SRD_CONF_SAMPLERATE: | |
175 | self.samplerate = value; | |
176 | # The width of one UART bit in number of samples. | |
177 | self.bit_width = float(self.samplerate) / float(self.options['baudrate']) | |
178 | ||
179 | # Return true if we reached the middle of the desired bit, false otherwise. | |
180 | def reached_bit(self, rxtx, bitnum): | |
181 | # bitpos is the samplenumber which is in the middle of the | |
182 | # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit | |
183 | # (if used) or the first stop bit, and so on). | |
184 | bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) | |
185 | bitpos += bitnum * self.bit_width | |
186 | if self.samplenum >= bitpos: | |
187 | return True | |
188 | return False | |
189 | ||
190 | def reached_bit_last(self, rxtx, bitnum): | |
191 | bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) | |
192 | if self.samplenum >= bitpos: | |
193 | return True | |
194 | return False | |
195 | ||
196 | def wait_for_start_bit(self, rxtx, old_signal, signal): | |
197 | # The start bit is always 0 (low). As the idle UART (and the stop bit) | |
198 | # level is 1 (high), the beginning of a start bit is a falling edge. | |
199 | if not (old_signal == 1 and signal == 0): | |
200 | return | |
201 | ||
202 | # Save the sample number where the start bit begins. | |
203 | self.frame_start[rxtx] = self.samplenum | |
204 | ||
205 | self.state[rxtx] = 'GET START BIT' | |
206 | ||
207 | def get_start_bit(self, rxtx, signal): | |
208 | # Skip samples until we're in the middle of the start bit. | |
209 | if not self.reached_bit(rxtx, 0): | |
210 | return | |
211 | ||
212 | self.startbit[rxtx] = signal | |
213 | ||
214 | # The startbit must be 0. If not, we report an error. | |
215 | if self.startbit[rxtx] != 0: | |
216 | self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) | |
217 | # TODO: Abort? Ignore rest of the frame? | |
218 | ||
219 | self.cur_data_bit[rxtx] = 0 | |
220 | self.databyte[rxtx] = 0 | |
221 | self.startsample[rxtx] = -1 | |
222 | ||
223 | self.state[rxtx] = 'GET DATA BITS' | |
224 | ||
225 | self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) | |
226 | self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) | |
227 | ||
228 | def get_data_bits(self, rxtx, signal): | |
229 | # Skip samples until we're in the middle of the desired data bit. | |
230 | if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): | |
231 | return | |
232 | ||
233 | # Save the sample number of the middle of the first data bit. | |
234 | if self.startsample[rxtx] == -1: | |
235 | self.startsample[rxtx] = self.samplenum | |
236 | ||
237 | # Get the next data bit in LSB-first or MSB-first fashion. | |
238 | if self.options['bit_order'] == 'lsb-first': | |
239 | self.databyte[rxtx] >>= 1 | |
240 | self.databyte[rxtx] |= \ | |
241 | (signal << (self.options['num_data_bits'] - 1)) | |
242 | elif self.options['bit_order'] == 'msb-first': | |
243 | self.databyte[rxtx] <<= 1 | |
244 | self.databyte[rxtx] |= (signal << 0) | |
245 | else: | |
246 | raise Exception('Invalid bit order value: %s', | |
247 | self.options['bit_order']) | |
248 | ||
249 | self.putg([rxtx + 12, ['%d' % signal]]) | |
250 | ||
251 | # Store individual data bits and their start/end samplenumbers. | |
252 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
253 | self.databits[rxtx].append([signal, s - halfbit, s + halfbit]) | |
254 | ||
255 | # Return here, unless we already received all data bits. | |
256 | if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: | |
257 | self.cur_data_bit[rxtx] += 1 | |
258 | return | |
259 | ||
260 | self.state[rxtx] = 'GET PARITY BIT' | |
261 | ||
262 | self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]]) | |
263 | self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]]) | |
264 | ||
265 | b, f = self.databyte[rxtx], self.options['format'] | |
266 | if f == 'ascii': | |
267 | c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b | |
268 | self.putx(rxtx, [rxtx, [c]]) | |
269 | elif f == 'dec': | |
270 | self.putx(rxtx, [rxtx, [str(b)]]) | |
271 | elif f == 'hex': | |
272 | self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]]) | |
273 | elif f == 'oct': | |
274 | self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]]) | |
275 | elif f == 'bin': | |
276 | self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]]) | |
277 | else: | |
278 | raise Exception('Invalid data format option: %s' % f) | |
279 | ||
280 | self.putbin(rxtx, (rxtx, bytes([b]))) | |
281 | self.putbin(rxtx, (2, bytes([b]))) | |
282 | ||
283 | self.databits = [[], []] | |
284 | ||
285 | def get_parity_bit(self, rxtx, signal): | |
286 | # If no parity is used/configured, skip to the next state immediately. | |
287 | if self.options['parity_type'] == 'none': | |
288 | self.state[rxtx] = 'GET STOP BITS' | |
289 | return | |
290 | ||
291 | # Skip samples until we're in the middle of the parity bit. | |
292 | if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): | |
293 | return | |
294 | ||
295 | self.paritybit[rxtx] = signal | |
296 | ||
297 | self.state[rxtx] = 'GET STOP BITS' | |
298 | ||
299 | if parity_ok(self.options['parity_type'], self.paritybit[rxtx], | |
300 | self.databyte[rxtx], self.options['num_data_bits']): | |
301 | self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) | |
302 | self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']]) | |
303 | else: | |
304 | # TODO: Return expected/actual parity values. | |
305 | self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... | |
306 | self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) | |
307 | ||
308 | # TODO: Currently only supports 1 stop bit. | |
309 | def get_stop_bits(self, rxtx, signal): | |
310 | # Skip samples until we're in the middle of the stop bit(s). | |
311 | skip_parity = 0 if self.options['parity_type'] == 'none' else 1 | |
312 | b = self.options['num_data_bits'] + 1 + skip_parity | |
313 | if not self.reached_bit(rxtx, b): | |
314 | return | |
315 | ||
316 | self.stopbit1[rxtx] = signal | |
317 | ||
318 | # Stop bits must be 1. If not, we report an error. | |
319 | if self.stopbit1[rxtx] != 1: | |
320 | self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) | |
321 | self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']]) | |
322 | # TODO: Abort? Ignore the frame? Other? | |
323 | ||
324 | self.state[rxtx] = 'WAIT FOR START BIT' | |
325 | ||
326 | self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) | |
327 | self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) | |
328 | ||
329 | def decode(self, ss, es, data): | |
330 | if self.samplerate is None: | |
331 | raise Exception("Cannot decode without samplerate.") | |
332 | for (self.samplenum, pins) in data: | |
333 | ||
334 | # Note: Ignoring identical samples here for performance reasons | |
335 | # is not possible for this PD, at least not in the current state. | |
336 | # if self.oldpins == pins: | |
337 | # continue | |
338 | self.oldpins, (rx, tx) = pins, pins | |
339 | ||
340 | # Either RX or TX (but not both) can be omitted. | |
341 | has_pin = [rx in (0, 1), tx in (0, 1)] | |
342 | if has_pin == [False, False]: | |
343 | raise Exception('Either TX or RX (or both) pins required.') | |
344 | ||
345 | # State machine. | |
346 | for rxtx in (RX, TX): | |
347 | # Don't try to handle RX (or TX) if not supplied. | |
348 | if not has_pin[rxtx]: | |
349 | continue | |
350 | ||
351 | signal = rx if (rxtx == RX) else tx | |
352 | ||
353 | if self.state[rxtx] == 'WAIT FOR START BIT': | |
354 | self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) | |
355 | elif self.state[rxtx] == 'GET START BIT': | |
356 | self.get_start_bit(rxtx, signal) | |
357 | elif self.state[rxtx] == 'GET DATA BITS': | |
358 | self.get_data_bits(rxtx, signal) | |
359 | elif self.state[rxtx] == 'GET PARITY BIT': | |
360 | self.get_parity_bit(rxtx, signal) | |
361 | elif self.state[rxtx] == 'GET STOP BITS': | |
362 | self.get_stop_bits(rxtx, signal) | |
363 | else: | |
364 | raise Exception('Invalid state: %s' % self.state[rxtx]) | |
365 | ||
366 | # Save current RX/TX values for the next round. | |
367 | self.oldbit[rxtx] = signal | |
368 |