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1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
22 | import sigrokdecode as srd | |
23 | ||
24 | # Chip-select options | |
25 | ACTIVE_LOW = 0 | |
26 | ACTIVE_HIGH = 1 | |
27 | ||
28 | # Clock polarity options | |
29 | CPOL_0 = 0 # Clock is low when inactive | |
30 | CPOL_1 = 1 # Clock is high when inactive | |
31 | ||
32 | # Clock phase options | |
33 | CPHA_0 = 0 # Data is valid on the rising clock edge | |
34 | CPHA_1 = 1 # Data is valid on the falling clock edge | |
35 | ||
36 | # Bit order options | |
37 | MSB_FIRST = 0 | |
38 | LSB_FIRST = 1 | |
39 | ||
40 | # Annotation formats | |
41 | ANN_HEX = 0 | |
42 | ||
43 | class Decoder(srd.Decoder): | |
44 | id = 'spi' | |
45 | name = 'SPI' | |
46 | longname = 'Serial Peripheral Interface (SPI) bus' | |
47 | desc = '...desc...' | |
48 | longdesc = '...longdesc...' | |
49 | author = 'Gareth McMullin' | |
50 | email = 'gareth@blacksphere.co.nz' | |
51 | license = 'gplv2+' | |
52 | inputs = ['logic'] | |
53 | outputs = ['spi'] | |
54 | probes = [ | |
55 | {'id': 'mosi', 'name': 'MOSI', | |
56 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
57 | {'id': 'miso', 'name': 'MISO', | |
58 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
59 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, | |
60 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, | |
61 | ] | |
62 | options = { | |
63 | 'cs_active_low': ['CS# active low', ACTIVE_LOW], | |
64 | 'clock_polarity': ['Clock polarity', CPOL_0], | |
65 | 'clock_phase': ['Clock phase', CPHA_0], | |
66 | 'bit_order': ['Bit order within the SPI data', MSB_FIRST], | |
67 | 'word_size': ['Word size of SPI data', 8], # 1-64? | |
68 | } | |
69 | annotations = [ | |
70 | ['Hex', 'SPI data bytes in hex format'], | |
71 | ] | |
72 | ||
73 | def __init__(self): | |
74 | self.oldsck = 1 | |
75 | self.bitcount = 0 | |
76 | self.mosidata = 0 | |
77 | self.misodata = 0 | |
78 | self.bytesreceived = 0 | |
79 | self.samplenum = -1 | |
80 | ||
81 | # Set protocol decoder option defaults. | |
82 | self.cs_active_low = Decoder.options['cs_active_low'][1] | |
83 | self.clock_polarity = Decoder.options['clock_polarity'][1] | |
84 | self.clock_phase = Decoder.options['clock_phase'][1] | |
85 | self.bit_order = Decoder.options['bit_order'][1] | |
86 | self.word_size = Decoder.options['word_size'][1] | |
87 | ||
88 | def start(self, metadata): | |
89 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') | |
90 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') | |
91 | ||
92 | def report(self): | |
93 | return 'SPI: %d bytes received' % self.bytesreceived | |
94 | ||
95 | def decode(self, ss, es, data): | |
96 | # HACK! At the moment the number of probes is not handled correctly. | |
97 | # E.g. if an input file (-i foo.sr) has more than two probes enabled. | |
98 | # for (samplenum, (mosi, sck, x, y, z, a)) in data: | |
99 | # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: | |
100 | for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: | |
101 | ||
102 | self.samplenum += 1 # FIXME | |
103 | ||
104 | # Sample data on rising SCK edges. | |
105 | if sck == self.oldsck: | |
106 | continue | |
107 | self.oldsck = sck | |
108 | if sck == 0: | |
109 | continue | |
110 | ||
111 | # If this is the first bit, save its sample number. | |
112 | if self.bitcount == 0: | |
113 | self.start_sample = samplenum | |
114 | ||
115 | # Receive MOSI bit into our shift register. | |
116 | if self.bit_order == MSB_FIRST: | |
117 | self.mosidata |= mosi << (7 - self.bitcount) | |
118 | else: | |
119 | self.mosidata |= mosi << self.bitcount | |
120 | ||
121 | # Receive MISO bit into our shift register. | |
122 | if self.bit_order == MSB_FIRST: | |
123 | self.misodata |= miso << (7 - self.bitcount) | |
124 | else: | |
125 | self.misodata |= miso << self.bitcount | |
126 | ||
127 | self.bitcount += 1 | |
128 | ||
129 | # Continue to receive if not a byte yet. | |
130 | if self.bitcount != 8: | |
131 | continue | |
132 | ||
133 | self.put(self.start_sample, self.samplenum, self.out_proto, | |
134 | ['data', self.mosidata, self.misodata]) | |
135 | self.put(self.start_sample, self.samplenum, self.out_ann, | |
136 | [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, | |
137 | self.misodata)]]) | |
138 | ||
139 | # Reset decoder state. | |
140 | self.mosidata = 0 | |
141 | self.misodata = 0 | |
142 | self.bitcount = 0 | |
143 | ||
144 | # Keep stats for summary. | |
145 | self.bytesreceived += 1 | |
146 |