[libsigrokdecode.git] / decoders / rtc8564 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

# Return the specified BCD number (max. 8 bits) as integer.
def bcd2int(b):
    return (b & 0x0f) + ((b >> 4) * 10)

class Decoder(srd.Decoder):
    api_version = 1
    id = 'rtc8564'
    name = 'RTC-8564'
    longname = 'Epson RTC-8564 JE/NB'
    desc = 'Realtime clock module protocol.'
    license = 'gplv2+'
    inputs = ['i2c']
    outputs = ['rtc8564']
    probes = []
    optional_probes = [
        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
        {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
    ]
    options = {}
    annotations = [
        ['reg-0x00', 'Register 0x00'],
        ['reg-0x01', 'Register 0x01'],
        ['reg-0x02', 'Register 0x02'],
        ['reg-0x03', 'Register 0x03'],
        ['reg-0x04', 'Register 0x04'],
        ['reg-0x05', 'Register 0x05'],
        ['reg-0x06', 'Register 0x06'],
        ['reg-0x07', 'Register 0x07'],
        ['reg-0x08', 'Register 0x08'],
        ['read', 'Read date/time'],
        ['write', 'Write date/time'],
        ['bits', 'Bits'],
    ]
    annotation_rows = (
        ('bits', 'Bits', (11,)),
        ('regs', 'Registers', tuple(range(0, 8 + 1))),
        ('date-time', 'Date/time', (9, 10)),
    )

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        self.hours = -1
        self.minutes = -1
        self.seconds = -1
        self.days = -1
        self.months = -1
        self.years = -1

    def start(self):
        # self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def handle_reg_0x00(self, b): # Control register 1
        pass

    def handle_reg_0x01(self, b): # Control register 2
        ti_tp = 1 if (b & (1 << 4)) else 0
        af = 1 if (b & (1 << 3)) else 0
        tf = 1 if (b & (1 << 2)) else 0
        aie = 1 if (b & (1 << 1)) else 0
        tie = 1 if (b & (1 << 0)) else 0

        ann = ''

        s = 'repeated' if ti_tp else 'single-shot'
        ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
               'events\n' % (ti_tp, s)
        s = '' if af else 'no '
        ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
        s = '' if tf else 'no '
        ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
        s = 'enabled' if aie else 'prohibited'
        ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
               'occurs\n' % (aie, s)
        s = 'enabled' if tie else 'prohibited'
        ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
               'event occurs\n' % (tie, s)

        self.putx([1, [ann]])

    def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
        self.seconds = bcd2int(b & 0x7f)
        self.putx([2, ['Seconds: %d' % self.seconds]])
        vl = 1 if (b & (1 << 7)) else 0
        self.putx([11, ['Voltage low (VL) bit: %d' % vl]])

    def handle_reg_0x03(self, b): # Minutes
        self.minutes = bcd2int(b & 0x7f)
        self.putx([3, ['Minutes: %d' % self.minutes]])

    def handle_reg_0x04(self, b): # Hours
        self.hours = bcd2int(b & 0x3f)
        self.putx([4, ['Hours: %d' % self.hours]])

    def handle_reg_0x05(self, b): # Days
        self.days = bcd2int(b & 0x3f)
        self.putx([5, ['Days: %d' % self.days]])

    def handle_reg_0x06(self, b): # Day counter
        pass

    def handle_reg_0x07(self, b): # Months / century
        # TODO: Handle century bit.
        self.months = bcd2int(b & 0x1f)
        self.putx([7, ['Months: %d' % self.months]])

    def handle_reg_0x08(self, b): # Years
        self.years = bcd2int(b & 0xff)
        self.putx([8, ['Years: %d' % self.years]])

    def handle_reg_0x09(self, b): # Alarm, minute
        pass

    def handle_reg_0x0a(self, b): # Alarm, hour
        pass

    def handle_reg_0x0b(self, b): # Alarm, day
        pass

    def handle_reg_0x0c(self, b): # Alarm, weekday
        pass

    def handle_reg_0x0d(self, b): # CLKOUT output
        pass

    def handle_reg_0x0e(self, b): # Timer setting
        pass

    def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
        pass

    def decode(self, ss, es, data):
        cmd, databyte = data

        # Store the start/end samples of this I²C packet.
        self.ss, self.es = ss, es

        # State machine.
        if self.state == 'IDLE':
            # Wait for an I²C START condition.
            if cmd != 'START':
                return
            self.state = 'GET SLAVE ADDR'
            self.block_start_sample = ss
        elif self.state == 'GET SLAVE ADDR':
            # Wait for an address write operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd != 'ADDRESS WRITE':
                return
            self.state = 'GET REG ADDR'
        elif self.state == 'GET REG ADDR':
            # Wait for a data write (master selects the slave register).
            if cmd != 'DATA WRITE':
                return
            self.reg = databyte
            self.state = 'WRITE RTC REGS'
        elif self.state == 'WRITE RTC REGS':
            # If we see a Repeated Start here, it's probably an RTC read.
            if cmd == 'START REPEAT':
                self.state = 'READ RTC REGS'
                return
            # Otherwise: Get data bytes until a STOP condition occurs.
            if cmd == 'DATA WRITE':
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                # TODO: Handle read/write of only parts of these items.
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [9, ['Write date/time: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS':
            # Wait for an address read operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd == 'ADDRESS READ':
                self.state = 'READ RTC REGS2'
                return
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS2':
            if cmd == 'DATA READ':
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [10, ['Read date/time: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO?
        else:
            raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	import sigrokdecode as srd
	22
	23	# Return the specified BCD number (max. 8 bits) as integer.
	24	def bcd2int(b):
	25	return (b & 0x0f) + ((b >> 4) * 10)
	26
	27	class Decoder(srd.Decoder):
	28	api_version = 1
	29	id = 'rtc8564'
	30	name = 'RTC-8564'
	31	longname = 'Epson RTC-8564 JE/NB'
	32	desc = 'Realtime clock module protocol.'
	33	license = 'gplv2+'
	34	inputs = ['i2c']
	35	outputs = ['rtc8564']
	36	probes = []
	37	optional_probes = [
	38	{'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
	39	{'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
	40	{'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
	41	]
	42	options = {}
	43	annotations = [
	44	['reg-0x00', 'Register 0x00'],
	45	['reg-0x01', 'Register 0x01'],
	46	['reg-0x02', 'Register 0x02'],
	47	['reg-0x03', 'Register 0x03'],
	48	['reg-0x04', 'Register 0x04'],
	49	['reg-0x05', 'Register 0x05'],
	50	['reg-0x06', 'Register 0x06'],
	51	['reg-0x07', 'Register 0x07'],
	52	['reg-0x08', 'Register 0x08'],
	53	['read', 'Read date/time'],
	54	['write', 'Write date/time'],
	55	['bits', 'Bits'],
	56	]
	57	annotation_rows = (
	58	('bits', 'Bits', (11,)),
	59	('regs', 'Registers', tuple(range(0, 8 + 1))),
	60	('date-time', 'Date/time', (9, 10)),
	61	)
	62
	63	def __init__(self, **kwargs):
	64	self.state = 'IDLE'
	65	self.hours = -1
	66	self.minutes = -1
	67	self.seconds = -1
	68	self.days = -1
	69	self.months = -1
	70	self.years = -1
	71
	72	def start(self):
	73	# self.out_python = self.register(srd.OUTPUT_PYTHON)
	74	self.out_ann = self.register(srd.OUTPUT_ANN)
	75
	76	def putx(self, data):
	77	self.put(self.ss, self.es, self.out_ann, data)
	78
	79	def handle_reg_0x00(self, b): # Control register 1
	80	pass
	81
	82	def handle_reg_0x01(self, b): # Control register 2
	83	ti_tp = 1 if (b & (1 << 4)) else 0
	84	af = 1 if (b & (1 << 3)) else 0
	85	tf = 1 if (b & (1 << 2)) else 0
	86	aie = 1 if (b & (1 << 1)) else 0
	87	tie = 1 if (b & (1 << 0)) else 0
	88
	89	ann = ''
	90
	91	s = 'repeated' if ti_tp else 'single-shot'
	92	ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
	93	'events\n' % (ti_tp, s)
	94	s = '' if af else 'no '
	95	ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
	96	s = '' if tf else 'no '
	97	ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
	98	s = 'enabled' if aie else 'prohibited'
	99	ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
	100	'occurs\n' % (aie, s)
	101	s = 'enabled' if tie else 'prohibited'
	102	ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
	103	'event occurs\n' % (tie, s)
	104
	105	self.putx([1, [ann]])
	106
	107	def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
	108	self.seconds = bcd2int(b & 0x7f)
	109	self.putx([2, ['Seconds: %d' % self.seconds]])
	110	vl = 1 if (b & (1 << 7)) else 0
	111	self.putx([11, ['Voltage low (VL) bit: %d' % vl]])
	112
	113	def handle_reg_0x03(self, b): # Minutes
	114	self.minutes = bcd2int(b & 0x7f)
	115	self.putx([3, ['Minutes: %d' % self.minutes]])
	116
	117	def handle_reg_0x04(self, b): # Hours
	118	self.hours = bcd2int(b & 0x3f)
	119	self.putx([4, ['Hours: %d' % self.hours]])
	120
	121	def handle_reg_0x05(self, b): # Days
	122	self.days = bcd2int(b & 0x3f)
	123	self.putx([5, ['Days: %d' % self.days]])
	124
	125	def handle_reg_0x06(self, b): # Day counter
	126	pass
	127
	128	def handle_reg_0x07(self, b): # Months / century
	129	# TODO: Handle century bit.
	130	self.months = bcd2int(b & 0x1f)
	131	self.putx([7, ['Months: %d' % self.months]])
	132
	133	def handle_reg_0x08(self, b): # Years
	134	self.years = bcd2int(b & 0xff)
	135	self.putx([8, ['Years: %d' % self.years]])
	136
	137	def handle_reg_0x09(self, b): # Alarm, minute
	138	pass
	139
	140	def handle_reg_0x0a(self, b): # Alarm, hour
	141	pass
	142
	143	def handle_reg_0x0b(self, b): # Alarm, day
	144	pass
	145
	146	def handle_reg_0x0c(self, b): # Alarm, weekday
	147	pass
	148
	149	def handle_reg_0x0d(self, b): # CLKOUT output
	150	pass
	151
	152	def handle_reg_0x0e(self, b): # Timer setting
	153	pass
	154
	155	def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
	156	pass
	157
	158	def decode(self, ss, es, data):
	159	cmd, databyte = data
	160
	161	# Store the start/end samples of this I²C packet.
	162	self.ss, self.es = ss, es
	163
	164	# State machine.
	165	if self.state == 'IDLE':
	166	# Wait for an I²C START condition.
	167	if cmd != 'START':
	168	return
	169	self.state = 'GET SLAVE ADDR'
	170	self.block_start_sample = ss
	171	elif self.state == 'GET SLAVE ADDR':
	172	# Wait for an address write operation.
	173	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	174	if cmd != 'ADDRESS WRITE':
	175	return
	176	self.state = 'GET REG ADDR'
	177	elif self.state == 'GET REG ADDR':
	178	# Wait for a data write (master selects the slave register).
	179	if cmd != 'DATA WRITE':
	180	return
	181	self.reg = databyte
	182	self.state = 'WRITE RTC REGS'
	183	elif self.state == 'WRITE RTC REGS':
	184	# If we see a Repeated Start here, it's probably an RTC read.
	185	if cmd == 'START REPEAT':
	186	self.state = 'READ RTC REGS'
	187	return
	188	# Otherwise: Get data bytes until a STOP condition occurs.
	189	if cmd == 'DATA WRITE':
	190	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	191	handle_reg(databyte)
	192	self.reg += 1
	193	# TODO: Check for NACK!
	194	elif cmd == 'STOP':
	195	# TODO: Handle read/write of only parts of these items.
	196	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	197	self.years, self.hours, self.minutes, self.seconds)
	198	self.put(self.block_start_sample, es, self.out_ann,
	199	[9, ['Write date/time: %s' % d]])
	200	self.state = 'IDLE'
	201	else:
	202	pass # TODO
	203	elif self.state == 'READ RTC REGS':
	204	# Wait for an address read operation.
	205	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	206	if cmd == 'ADDRESS READ':
	207	self.state = 'READ RTC REGS2'
	208	return
	209	else:
	210	pass # TODO
	211	elif self.state == 'READ RTC REGS2':
	212	if cmd == 'DATA READ':
	213	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	214	handle_reg(databyte)
	215	self.reg += 1
	216	# TODO: Check for NACK!
	217	elif cmd == 'STOP':
	218	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	219	self.years, self.hours, self.minutes, self.seconds)
	220	self.put(self.block_start_sample, es, self.out_ann,
	221	[10, ['Read date/time: %s' % d]])
	222	self.state = 'IDLE'
	223	else:
	224	pass # TODO?
	225	else:
	226	raise Exception('Invalid state: %s' % self.state)
	227