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2dc6d41c | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
2dc6d41c UH |
3 | ## |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
7d4b5fac | 5 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
2dc6d41c UH |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
22 | # USB signalling (low-speed and full-speed) protocol decoder | |
23 | ||
24 | import sigrokdecode as srd | |
25 | ||
a56b8fe1 UH |
26 | ''' |
27 | Protocol output format: | |
28 | ||
29 | Packet: | |
30 | [<ptype>, <pdata>] | |
31 | ||
32 | <ptype>, <pdata>: | |
33 | - 'SOP', None | |
34 | - 'SYM', <sym> | |
35 | - 'BIT', <bit> | |
36 | - 'STUFF BIT', None | |
37 | - 'EOP', None | |
a56b8fe1 UH |
38 | |
39 | <sym>: | |
40 | - 'J', 'K', 'SE0', or 'SE1' | |
41 | ||
42 | <bit>: | |
43 | - 0 or 1 | |
44 | - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'. | |
a56b8fe1 UH |
45 | ''' |
46 | ||
d1970f14 | 47 | # Low-/full-speed symbols. |
2dc6d41c | 48 | # Note: Low-speed J and K are inverted compared to the full-speed J and K! |
7dc75721 UH |
49 | symbols = { |
50 | 'low-speed': { | |
2dc6d41c UH |
51 | # (<dp>, <dm>): <symbol/state> |
52 | (0, 0): 'SE0', | |
53 | (1, 0): 'K', | |
54 | (0, 1): 'J', | |
55 | (1, 1): 'SE1', | |
7dc75721 UH |
56 | }, |
57 | 'full-speed': { | |
2dc6d41c UH |
58 | # (<dp>, <dm>): <symbol/state> |
59 | (0, 0): 'SE0', | |
60 | (1, 0): 'J', | |
61 | (0, 1): 'K', | |
62 | (1, 1): 'SE1', | |
7dc75721 | 63 | }, |
2dc6d41c UH |
64 | } |
65 | ||
5bb55598 UH |
66 | bitrates = { |
67 | 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%) | |
68 | 'full-speed': 12000000, # 12Mb/s (+/- 0.25%) | |
69 | } | |
70 | ||
2dc6d41c UH |
71 | class Decoder(srd.Decoder): |
72 | api_version = 1 | |
73 | id = 'usb_signalling' | |
74 | name = 'USB signalling' | |
75 | longname = 'Universal Serial Bus (LS/FS) signalling' | |
9e1437a0 | 76 | desc = 'USB (low-speed and full-speed) signalling protocol.' |
2dc6d41c UH |
77 | license = 'gplv2+' |
78 | inputs = ['logic'] | |
79 | outputs = ['usb_signalling'] | |
80 | probes = [ | |
81 | {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'}, | |
82 | {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, | |
83 | ] | |
84 | optional_probes = [] | |
85 | options = { | |
86 | 'signalling': ['Signalling', 'full-speed'], | |
87 | } | |
88 | annotations = [ | |
9059125f | 89 | ['sym', 'Symbol'], |
edad8134 UH |
90 | ['sop', 'Start of packet (SOP)'], |
91 | ['eop', 'End of packet (EOP)'], | |
92 | ['bit', 'Bit'], | |
93 | ['stuffbit', 'Stuff bit'], | |
2dc6d41c UH |
94 | ] |
95 | ||
96 | def __init__(self): | |
f372d597 | 97 | self.samplerate = None |
d1970f14 | 98 | self.oldsym = 'J' # The "idle" state is J. |
fdd5ee5e UH |
99 | self.ss_sop = None |
100 | self.ss_block = None | |
2dc6d41c | 101 | self.samplenum = 0 |
2dc6d41c | 102 | self.syms = [] |
5bb55598 UH |
103 | self.bitrate = None |
104 | self.bitwidth = None | |
d1970f14 UH |
105 | self.bitnum = 0 |
106 | self.samplenum_target = None | |
2fcd7c22 | 107 | self.oldpins = None |
d1970f14 UH |
108 | self.consecutive_ones = 0 |
109 | self.state = 'IDLE' | |
2dc6d41c | 110 | |
f372d597 | 111 | def start(self): |
be465111 BV |
112 | self.out_proto = self.register(srd.OUTPUT_PYTHON) |
113 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
f372d597 BV |
114 | |
115 | def metadata(self, key, value): | |
116 | if key == srd.SRD_CONF_SAMPLERATE: | |
117 | self.samplerate = value | |
118 | self.bitrate = bitrates[self.options['signalling']] | |
119 | self.bitwidth = float(self.samplerate) / float(self.bitrate) | |
120 | self.halfbit = int(self.bitwidth / 2) | |
2dc6d41c | 121 | |
d1970f14 | 122 | def putpx(self, data): |
7d4b5fac UH |
123 | self.put(self.samplenum, self.samplenum, self.out_proto, data) |
124 | ||
125 | def putx(self, data): | |
126 | self.put(self.samplenum, self.samplenum, self.out_ann, data) | |
127 | ||
fdd5ee5e UH |
128 | def putpm(self, data): |
129 | s, h = self.samplenum, self.halfbit | |
9059125f | 130 | self.put(self.ss_block - h, s + h, self.out_proto, data) |
fdd5ee5e UH |
131 | |
132 | def putm(self, data): | |
133 | s, h = self.samplenum, self.halfbit | |
9059125f | 134 | self.put(self.ss_block - h, s + h, self.out_ann, data) |
fdd5ee5e | 135 | |
d1970f14 | 136 | def putpb(self, data): |
fdd5ee5e UH |
137 | s, h = self.samplenum, self.halfbit |
138 | self.put(s - h, s + h, self.out_proto, data) | |
d1970f14 UH |
139 | |
140 | def putb(self, data): | |
fdd5ee5e UH |
141 | s, h = self.samplenum, self.halfbit |
142 | self.put(s - h, s + h, self.out_ann, data) | |
d1970f14 UH |
143 | |
144 | def set_new_target_samplenum(self): | |
145 | bitpos = self.ss_sop + (self.bitwidth / 2) | |
146 | bitpos += self.bitnum * self.bitwidth | |
147 | self.samplenum_target = int(bitpos) | |
148 | ||
149 | def wait_for_sop(self, sym): | |
150 | # Wait for a Start of Packet (SOP), i.e. a J->K symbol change. | |
151 | if sym != 'K': | |
152 | self.oldsym = sym | |
153 | return | |
154 | self.ss_sop = self.samplenum | |
155 | self.set_new_target_samplenum() | |
156 | self.putpx(['SOP', None]) | |
edad8134 | 157 | self.putx([1, ['SOP']]) |
d1970f14 UH |
158 | self.state = 'GET BIT' |
159 | ||
160 | def handle_bit(self, sym, b): | |
161 | if self.consecutive_ones == 6 and b == '0': | |
9059125f | 162 | # Stuff bit. |
a56b8fe1 | 163 | self.putpb(['STUFF BIT', None]) |
edad8134 | 164 | self.putb([4, ['SB: %s/%s' % (sym, b)]]) |
d1970f14 UH |
165 | self.consecutive_ones = 0 |
166 | else: | |
9059125f | 167 | # Normal bit (not a stuff bit). |
a56b8fe1 | 168 | self.putpb(['BIT', b]) |
edad8134 | 169 | self.putb([3, ['%s/%s' % (sym, b)]]) |
d1970f14 UH |
170 | if b == '1': |
171 | self.consecutive_ones += 1 | |
172 | else: | |
173 | self.consecutive_ones = 0 | |
174 | ||
175 | def get_eop(self, sym): | |
176 | # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J. | |
177 | self.syms.append(sym) | |
178 | self.putpb(['SYM', sym]) | |
179 | self.putb([0, ['%s' % sym]]) | |
180 | self.bitnum += 1 | |
181 | self.set_new_target_samplenum() | |
182 | self.oldsym = sym | |
183 | if self.syms[-2:] == ['SE0', 'J']: | |
9059125f | 184 | # Got an EOP. |
fdd5ee5e UH |
185 | self.putpm(['EOP', None]) |
186 | self.putm([2, ['EOP']]) | |
9059125f | 187 | self.bitnum, self.syms, self.state = 0, [], 'IDLE' |
d1970f14 UH |
188 | self.consecutive_ones = 0 |
189 | ||
190 | def get_bit(self, sym): | |
191 | if sym == 'SE0': | |
192 | # Start of an EOP. Change state, run get_eop() for this bit. | |
193 | self.state = 'GET EOP' | |
fdd5ee5e | 194 | self.ss_block = self.samplenum |
d1970f14 UH |
195 | self.get_eop(sym) |
196 | return | |
197 | self.syms.append(sym) | |
198 | self.putpb(['SYM', sym]) | |
199 | b = '0' if self.oldsym != sym else '1' | |
200 | self.handle_bit(sym, b) | |
201 | self.bitnum += 1 | |
202 | self.set_new_target_samplenum() | |
203 | self.oldsym = sym | |
204 | ||
2dc6d41c | 205 | def decode(self, ss, es, data): |
f372d597 BV |
206 | if self.samplerate is None: |
207 | raise Exception("Cannot decode without samplerate.") | |
2fcd7c22 | 208 | for (self.samplenum, pins) in data: |
d1970f14 UH |
209 | # State machine. |
210 | if self.state == 'IDLE': | |
211 | # Ignore identical samples early on (for performance reasons). | |
212 | if self.oldpins == pins: | |
213 | continue | |
214 | self.oldpins = pins | |
215 | sym = symbols[self.options['signalling']][tuple(pins)] | |
216 | self.wait_for_sop(sym) | |
217 | elif self.state in ('GET BIT', 'GET EOP'): | |
218 | # Wait until we're in the middle of the desired bit. | |
219 | if self.samplenum < self.samplenum_target: | |
220 | continue | |
221 | sym = symbols[self.options['signalling']][tuple(pins)] | |
222 | if self.state == 'GET BIT': | |
223 | self.get_bit(sym) | |
224 | elif self.state == 'GET EOP': | |
225 | self.get_eop(sym) | |
2dc6d41c | 226 | else: |
d1970f14 | 227 | raise Exception('Invalid state: %s' % self.state) |
2dc6d41c | 228 |