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f44d2db2 UH |
1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4a04ece4 | 4 | ## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> |
f44d2db2 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # | |
22 | # UART protocol decoder | |
23 | # | |
24 | ||
6efe1e11 UH |
25 | # |
26 | # Universal Asynchronous Receiver Transmitter (UART) is a simple serial | |
27 | # communication protocol which allows two devices to talk to each other. | |
28 | # | |
29 | # It uses just two data signals and a ground (GND) signal: | |
30 | # - RX/RXD: Receive signal | |
31 | # - TX/TXD: Transmit signal | |
32 | # | |
33 | # The protocol is asynchronous, i.e., there is no dedicated clock signal. | |
34 | # Rather, both devices have to agree on a baudrate (number of bits to be | |
35 | # transmitted per second) beforehand. Baudrates can be arbitrary in theory, | |
36 | # but usually the choice is limited by the hardware UARTs that are used. | |
37 | # Common values are 9600 or 115200. | |
38 | # | |
39 | # The protocol allows full-duplex transmission, i.e. both devices can send | |
40 | # data at the same time. However, unlike SPI (which is always full-duplex, | |
41 | # i.e., each send operation is automatically also a receive operation), UART | |
42 | # allows one-way communication, too. In such a case only one signal (and GND) | |
43 | # is required. | |
44 | # | |
45 | # The data is sent over the TX line in so-called 'frames', which consist of: | |
46 | # - Exactly one start bit (always 0/low). | |
47 | # - Between 5 and 9 data bits. | |
48 | # - An (optional) parity bit. | |
49 | # - One or more stop bit(s). | |
50 | # | |
51 | # The idle state of the RX/TX line is 1/high. As the start bit is 0/low, the | |
52 | # receiver can continually monitor its RX line for a falling edge, in order | |
53 | # to detect the start bit. | |
54 | # | |
55 | # Once detected, it can (due to the agreed-upon baudrate and thus the known | |
56 | # width/duration of one UART bit) sample the state of the RX line "in the | |
57 | # middle" of each (start/data/parity/stop) bit it wants to analyze. | |
58 | # | |
59 | # It is configurable whether there is a parity bit in a frame, and if yes, | |
60 | # which type of parity is used: | |
61 | # - None: No parity bit is included. | |
62 | # - Odd: The number of 1 bits in the data (and parity bit itself) is odd. | |
63 | # - Even: The number of 1 bits in the data (and parity bit itself) is even. | |
64 | # - Mark/one: The parity bit is always 1/high (also called 'mark state'). | |
65 | # - Space/zero: The parity bit is always 0/low (also called 'space state'). | |
66 | # | |
67 | # It is also configurable how many stop bits are to be used: | |
68 | # - 1 stop bit (most common case) | |
69 | # - 2 stop bits | |
70 | # - 1.5 stop bits (i.e., one stop bit, but 1.5 times the UART bit width) | |
71 | # - 0.5 stop bits (i.e., one stop bit, but 0.5 times the UART bit width) | |
72 | # | |
73 | # The bit order of the 5-9 data bits is LSB-first. | |
74 | # | |
75 | # Possible special cases: | |
76 | # - One or both data lines could be inverted, which also means that the idle | |
77 | # state of the signal line(s) is low instead of high. | |
78 | # - Only the data bits on one or both data lines (and the parity bit) could | |
79 | # be inverted (but the start/stop bits remain non-inverted). | |
80 | # - The bit order could be MSB-first instead of LSB-first. | |
81 | # - The baudrate could change in the middle of the communication. This only | |
82 | # happens in very special cases, and can only work if both devices know | |
83 | # to which baudrate they are to switch, and when. | |
84 | # - Theoretically, the baudrate on RX and the one on TX could also be | |
85 | # different, but that's a very obscure case and probably doesn't happen | |
86 | # very often in practice. | |
87 | # | |
88 | # Error conditions: | |
89 | # - If there is a parity bit, but it doesn't match the expected parity, | |
90 | # this is called a 'parity error'. | |
91 | # - If there are no stop bit(s), that's called a 'frame error'. | |
92 | # | |
93 | # More information: | |
94 | # TODO: URLs | |
95 | # | |
96 | ||
61132abd UH |
97 | # |
98 | # Protocol output format: | |
61132abd | 99 | # |
97cca21f UH |
100 | # UART packet: |
101 | # [<packet-type>, <rxtx>, <packet-data>] | |
61132abd | 102 | # |
97cca21f | 103 | # This is the list of <packet-types>s and their respective <packet-data>: |
61132abd UH |
104 | # - T_START: The data is the (integer) value of the start bit (0 or 1). |
105 | # - T_DATA: The data is the (integer) value of the UART data. Valid values | |
106 | # range from 0 to 512 (as the data can be up to 9 bits in size). | |
107 | # - T_PARITY: The data is the (integer) value of the parity bit (0 or 1). | |
108 | # - T_STOP: The data is the (integer) value of the stop bit (0 or 1). | |
109 | # - T_INVALID_START: The data is the (integer) value of the start bit (0 or 1). | |
110 | # - T_INVALID_STOP: The data is the (integer) value of the stop bit (0 or 1). | |
111 | # - T_PARITY_ERROR: The data is a tuple with two entries. The first one is | |
112 | # the expected parity value, the second is the actual parity value. | |
113 | # | |
97cca21f | 114 | # The <rxtx> field is 0 for RX packets, 1 for TX packets. |
61132abd UH |
115 | # |
116 | ||
677d597b | 117 | import sigrokdecode as srd |
f44d2db2 UH |
118 | |
119 | # States | |
120 | WAIT_FOR_START_BIT = 0 | |
121 | GET_START_BIT = 1 | |
122 | GET_DATA_BITS = 2 | |
123 | GET_PARITY_BIT = 3 | |
124 | GET_STOP_BITS = 4 | |
125 | ||
97cca21f UH |
126 | # Used for differentiating between the two data directions. |
127 | RX = 0 | |
128 | TX = 1 | |
129 | ||
f44d2db2 UH |
130 | # Parity options |
131 | PARITY_NONE = 0 | |
132 | PARITY_ODD = 1 | |
133 | PARITY_EVEN = 2 | |
134 | PARITY_ZERO = 3 | |
135 | PARITY_ONE = 4 | |
136 | ||
137 | # Stop bit options | |
138 | STOP_BITS_0_5 = 0 | |
139 | STOP_BITS_1 = 1 | |
140 | STOP_BITS_1_5 = 2 | |
141 | STOP_BITS_2 = 3 | |
142 | ||
143 | # Bit order options | |
144 | LSB_FIRST = 0 | |
145 | MSB_FIRST = 1 | |
146 | ||
1bb57ab8 UH |
147 | # Annotation feed formats |
148 | ANN_ASCII = 0 | |
149 | ANN_DEC = 1 | |
150 | ANN_HEX = 2 | |
151 | ANN_OCT = 3 | |
152 | ANN_BITS = 4 | |
f44d2db2 | 153 | |
61132abd UH |
154 | # Protocol output packet types |
155 | T_START = 0 | |
156 | T_DATA = 1 | |
157 | T_PARITY = 2 | |
158 | T_STOP = 3 | |
159 | T_INVALID_START = 4 | |
160 | T_INVALID_STOP = 5 | |
161 | T_PARITY_ERROR = 6 | |
162 | ||
f44d2db2 UH |
163 | # Given a parity type to check (odd, even, zero, one), the value of the |
164 | # parity bit, the value of the data, and the length of the data (5-9 bits, | |
165 | # usually 8 bits) return True if the parity is correct, False otherwise. | |
166 | # PARITY_NONE is _not_ allowed as value for 'parity_type'. | |
167 | def parity_ok(parity_type, parity_bit, data, num_data_bits): | |
168 | ||
169 | # Handle easy cases first (parity bit is always 1 or 0). | |
170 | if parity_type == PARITY_ZERO: | |
171 | return parity_bit == 0 | |
172 | elif parity_type == PARITY_ONE: | |
173 | return parity_bit == 1 | |
174 | ||
175 | # Count number of 1 (high) bits in the data (and the parity bit itself!). | |
176 | parity = bin(data).count('1') + parity_bit | |
177 | ||
178 | # Check for odd/even parity. | |
179 | if parity_type == PARITY_ODD: | |
180 | return (parity % 2) == 1 | |
181 | elif parity_type == PARITY_EVEN: | |
182 | return (parity % 2) == 0 | |
183 | else: | |
184 | raise Exception('Invalid parity type: %d' % parity_type) | |
185 | ||
677d597b | 186 | class Decoder(srd.Decoder): |
a2c2afd9 | 187 | api_version = 1 |
f44d2db2 UH |
188 | id = 'uart' |
189 | name = 'UART' | |
3d3da57d | 190 | longname = 'Universal Asynchronous Receiver/Transmitter' |
f44d2db2 UH |
191 | desc = 'Universal Asynchronous Receiver/Transmitter (UART)' |
192 | longdesc = 'TODO.' | |
f44d2db2 UH |
193 | license = 'gplv2+' |
194 | inputs = ['logic'] | |
195 | outputs = ['uart'] | |
29ed0f4c | 196 | probes = [ |
f44d2db2 UH |
197 | # Allow specifying only one of the signals, e.g. if only one data |
198 | # direction exists (or is relevant). | |
29ed0f4c UH |
199 | {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, |
200 | {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, | |
201 | ] | |
decde15e | 202 | extra_probes = [] |
f44d2db2 | 203 | options = { |
97cca21f | 204 | 'baudrate': ['Baud rate', 115200], |
f44d2db2 | 205 | 'num_data_bits': ['Data bits', 8], # Valid: 5-9. |
4a04ece4 UH |
206 | 'parity': ['Parity', PARITY_NONE], # TODO: Rename to parity_type. |
207 | 'parity_check': ['Check parity', True], # TODO: Bool supported? | |
f44d2db2 UH |
208 | 'num_stop_bits': ['Stop bit(s)', STOP_BITS_1], |
209 | 'bit_order': ['Bit order', LSB_FIRST], | |
f44d2db2 | 210 | # TODO: Options to invert the signal(s). |
f44d2db2 | 211 | } |
e97b6ef5 | 212 | annotations = [ |
97cca21f UH |
213 | ['ASCII', 'Data bytes as ASCII characters'], |
214 | ['Decimal', 'Databytes as decimal, integer values'], | |
215 | ['Hex', 'Data bytes in hex format'], | |
216 | ['Octal', 'Data bytes as octal numbers'], | |
217 | ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'], | |
1bb57ab8 | 218 | ] |
f44d2db2 | 219 | |
97cca21f UH |
220 | def putx(self, rxtx, data): |
221 | self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data) | |
222 | ||
f44d2db2 | 223 | def __init__(self, **kwargs): |
f44d2db2 | 224 | self.samplenum = 0 |
97cca21f UH |
225 | self.frame_start = [-1, -1] |
226 | self.startbit = [-1, -1] | |
227 | self.cur_data_bit = [0, 0] | |
228 | self.databyte = [0, 0] | |
229 | self.stopbit1 = [-1, -1] | |
230 | self.startsample = [-1, -1] | |
f44d2db2 UH |
231 | |
232 | # Initial state. | |
97cca21f | 233 | self.state = [WAIT_FOR_START_BIT, WAIT_FOR_START_BIT] |
f44d2db2 | 234 | |
97cca21f | 235 | self.oldbit = [None, None] |
f44d2db2 UH |
236 | |
237 | def start(self, metadata): | |
f44d2db2 | 238 | self.samplerate = metadata['samplerate'] |
56202222 UH |
239 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart') |
240 | self.out_ann = self.add(srd.OUTPUT_ANN, 'uart') | |
f44d2db2 | 241 | |
f44d2db2 | 242 | # The width of one UART bit in number of samples. |
4a04ece4 UH |
243 | self.bit_width = \ |
244 | float(self.samplerate) / float(self.options['baudrate']) | |
f44d2db2 UH |
245 | |
246 | def report(self): | |
247 | pass | |
248 | ||
249 | # Return true if we reached the middle of the desired bit, false otherwise. | |
97cca21f | 250 | def reached_bit(self, rxtx, bitnum): |
f44d2db2 UH |
251 | # bitpos is the samplenumber which is in the middle of the |
252 | # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit | |
253 | # (if used) or the first stop bit, and so on). | |
97cca21f | 254 | bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) |
f44d2db2 UH |
255 | bitpos += bitnum * self.bit_width |
256 | if self.samplenum >= bitpos: | |
257 | return True | |
258 | return False | |
259 | ||
97cca21f UH |
260 | def reached_bit_last(self, rxtx, bitnum): |
261 | bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) | |
f44d2db2 UH |
262 | if self.samplenum >= bitpos: |
263 | return True | |
264 | return False | |
265 | ||
97cca21f | 266 | def wait_for_start_bit(self, rxtx, old_signal, signal): |
f44d2db2 UH |
267 | # The start bit is always 0 (low). As the idle UART (and the stop bit) |
268 | # level is 1 (high), the beginning of a start bit is a falling edge. | |
269 | if not (old_signal == 1 and signal == 0): | |
270 | return | |
271 | ||
272 | # Save the sample number where the start bit begins. | |
97cca21f | 273 | self.frame_start[rxtx] = self.samplenum |
f44d2db2 | 274 | |
97cca21f | 275 | self.state[rxtx] = GET_START_BIT |
f44d2db2 | 276 | |
97cca21f | 277 | def get_start_bit(self, rxtx, signal): |
f44d2db2 | 278 | # Skip samples until we're in the middle of the start bit. |
97cca21f | 279 | if not self.reached_bit(rxtx, 0): |
1bb57ab8 | 280 | return |
f44d2db2 | 281 | |
97cca21f | 282 | self.startbit[rxtx] = signal |
f44d2db2 | 283 | |
5cc4b6a0 | 284 | # The startbit must be 0. If not, we report an error. |
97cca21f UH |
285 | if self.startbit[rxtx] != 0: |
286 | self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, | |
287 | [T_INVALID_START, rxtx, self.startbit[rxtx]]) | |
5cc4b6a0 | 288 | # TODO: Abort? Ignore rest of the frame? |
f44d2db2 | 289 | |
97cca21f UH |
290 | self.cur_data_bit[rxtx] = 0 |
291 | self.databyte[rxtx] = 0 | |
292 | self.startsample[rxtx] = -1 | |
f44d2db2 | 293 | |
97cca21f | 294 | self.state[rxtx] = GET_DATA_BITS |
f44d2db2 | 295 | |
97cca21f UH |
296 | self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, |
297 | [T_START, rxtx, self.startbit[rxtx]]) | |
298 | self.put(self.frame_start[rxtx], self.samplenum, self.out_ann, | |
5cc4b6a0 | 299 | [ANN_ASCII, ['Start bit', 'Start', 'S']]) |
f44d2db2 | 300 | |
97cca21f | 301 | def get_data_bits(self, rxtx, signal): |
f44d2db2 | 302 | # Skip samples until we're in the middle of the desired data bit. |
97cca21f | 303 | if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): |
1bb57ab8 | 304 | return |
f44d2db2 UH |
305 | |
306 | # Save the sample number where the data byte starts. | |
97cca21f UH |
307 | if self.startsample[rxtx] == -1: |
308 | self.startsample[rxtx] = self.samplenum | |
f44d2db2 UH |
309 | |
310 | # Get the next data bit in LSB-first or MSB-first fashion. | |
4a04ece4 | 311 | if self.options['bit_order'] == LSB_FIRST: |
97cca21f | 312 | self.databyte[rxtx] >>= 1 |
4a04ece4 UH |
313 | self.databyte[rxtx] |= (signal << (self.options['num_data_bits'] - 1)) |
314 | elif self.options['bit_order'] == MSB_FIRST: | |
97cca21f UH |
315 | self.databyte[rxtx] <<= 1 |
316 | self.databyte[rxtx] |= (signal << 0) | |
f44d2db2 | 317 | else: |
4a04ece4 UH |
318 | raise Exception('Invalid bit order value: %d', |
319 | self.options['bit_order']) | |
f44d2db2 UH |
320 | |
321 | # Return here, unless we already received all data bits. | |
4a04ece4 UH |
322 | # TODO? Off-by-one? |
323 | if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: | |
97cca21f | 324 | self.cur_data_bit[rxtx] += 1 |
1bb57ab8 | 325 | return |
f44d2db2 | 326 | |
97cca21f | 327 | self.state[rxtx] = GET_PARITY_BIT |
f44d2db2 | 328 | |
97cca21f UH |
329 | self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto, |
330 | [T_DATA, rxtx, self.databyte[rxtx]]) | |
f44d2db2 | 331 | |
97cca21f UH |
332 | s = 'RX: ' if (rxtx == RX) else 'TX: ' |
333 | self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]]) | |
334 | self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]]) | |
335 | self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]), | |
336 | s + hex(self.databyte[rxtx])[2:]]]) | |
337 | self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]), | |
338 | s + oct(self.databyte[rxtx])[2:]]]) | |
339 | self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]), | |
340 | s + bin(self.databyte[rxtx])[2:]]]) | |
f44d2db2 | 341 | |
97cca21f | 342 | def get_parity_bit(self, rxtx, signal): |
f44d2db2 | 343 | # If no parity is used/configured, skip to the next state immediately. |
4a04ece4 | 344 | if self.options['parity'] == PARITY_NONE: |
97cca21f | 345 | self.state[rxtx] = GET_STOP_BITS |
1bb57ab8 | 346 | return |
f44d2db2 UH |
347 | |
348 | # Skip samples until we're in the middle of the parity bit. | |
4a04ece4 | 349 | if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): |
1bb57ab8 | 350 | return |
f44d2db2 | 351 | |
97cca21f | 352 | self.paritybit[rxtx] = signal |
f44d2db2 | 353 | |
97cca21f | 354 | self.state[rxtx] = GET_STOP_BITS |
f44d2db2 | 355 | |
4a04ece4 UH |
356 | if parity_ok(self.options['parity'], self.paritybit[rxtx], |
357 | self.databyte[rxtx], self.options['num_data_bits']): | |
f44d2db2 | 358 | # TODO: Fix range. |
1bb57ab8 | 359 | self.put(self.samplenum, self.samplenum, self.out_proto, |
97cca21f | 360 | [T_PARITY_BIT, rxtx, self.paritybit[rxtx]]) |
1bb57ab8 | 361 | self.put(self.samplenum, self.samplenum, self.out_ann, |
5cc4b6a0 | 362 | [ANN_ASCII, ['Parity bit', 'Parity', 'P']]) |
f44d2db2 | 363 | else: |
1bb57ab8 | 364 | # TODO: Fix range. |
61132abd | 365 | # TODO: Return expected/actual parity values. |
1bb57ab8 | 366 | self.put(self.samplenum, self.samplenum, self.out_proto, |
97cca21f | 367 | [T_PARITY_ERROR, rxtx, (0, 1)]) # FIXME: Dummy tuple... |
1bb57ab8 | 368 | self.put(self.samplenum, self.samplenum, self.out_ann, |
5cc4b6a0 | 369 | [ANN_ASCII, ['Parity error', 'Parity err', 'PE']]) |
f44d2db2 UH |
370 | |
371 | # TODO: Currently only supports 1 stop bit. | |
97cca21f | 372 | def get_stop_bits(self, rxtx, signal): |
f44d2db2 | 373 | # Skip samples until we're in the middle of the stop bit(s). |
4a04ece4 UH |
374 | skip_parity = 0 if self.options['parity'] == PARITY_NONE else 1 |
375 | b = self.options['num_data_bits'] + 1 + skip_parity | |
376 | if not self.reached_bit(rxtx, b): | |
1bb57ab8 | 377 | return |
f44d2db2 | 378 | |
97cca21f | 379 | self.stopbit1[rxtx] = signal |
f44d2db2 | 380 | |
5cc4b6a0 | 381 | # Stop bits must be 1. If not, we report an error. |
97cca21f UH |
382 | if self.stopbit1[rxtx] != 1: |
383 | self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, | |
384 | [T_INVALID_STOP, rxtx, self.stopbit1[rxtx]]) | |
5cc4b6a0 | 385 | # TODO: Abort? Ignore the frame? Other? |
f44d2db2 | 386 | |
97cca21f | 387 | self.state[rxtx] = WAIT_FOR_START_BIT |
f44d2db2 | 388 | |
f44d2db2 | 389 | # TODO: Fix range. |
1bb57ab8 | 390 | self.put(self.samplenum, self.samplenum, self.out_proto, |
97cca21f | 391 | [T_STOP, rxtx, self.stopbit1[rxtx]]) |
1bb57ab8 | 392 | self.put(self.samplenum, self.samplenum, self.out_ann, |
5cc4b6a0 | 393 | [ANN_ASCII, ['Stop bit', 'Stop', 'P']]) |
f44d2db2 | 394 | |
decde15e UH |
395 | def decode(self, ss, es, data): |
396 | # TODO: Either RX or TX could be omitted (optional probe). | |
97cca21f | 397 | for (samplenum, (rx, tx)) in data: |
f44d2db2 UH |
398 | |
399 | # TODO: Start counting at 0 or 1? Increase before or after? | |
400 | self.samplenum += 1 | |
401 | ||
402 | # First sample: Save RX/TX value. | |
97cca21f UH |
403 | if self.oldbit[RX] == None: |
404 | self.oldbit[RX] = rx | |
405 | continue | |
406 | if self.oldbit[TX] == None: | |
407 | self.oldbit[TX] = tx | |
f44d2db2 UH |
408 | continue |
409 | ||
f44d2db2 | 410 | # State machine. |
97cca21f UH |
411 | for rxtx in (RX, TX): |
412 | signal = rx if (rxtx == RX) else tx | |
413 | ||
414 | if self.state[rxtx] == WAIT_FOR_START_BIT: | |
415 | self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) | |
416 | elif self.state[rxtx] == GET_START_BIT: | |
417 | self.get_start_bit(rxtx, signal) | |
418 | elif self.state[rxtx] == GET_DATA_BITS: | |
419 | self.get_data_bits(rxtx, signal) | |
420 | elif self.state[rxtx] == GET_PARITY_BIT: | |
421 | self.get_parity_bit(rxtx, signal) | |
422 | elif self.state[rxtx] == GET_STOP_BITS: | |
423 | self.get_stop_bits(rxtx, signal) | |
424 | else: | |
decde15e | 425 | raise Exception('Invalid state: %d' % self.state[rxtx]) |
97cca21f UH |
426 | |
427 | # Save current RX/TX values for the next round. | |
428 | self.oldbit[rxtx] = signal | |
f44d2db2 | 429 |