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92d1aba3 1##
50bd5d25 2## This file is part of the libsigrokdecode project.
92d1aba3 3##
ce0c47f3 4## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
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5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
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21import sigrokdecode as srd
22
23dacs = {
24 0: 'DACA',
25 1: 'DACB',
26 2: 'DACC',
27 3: 'DACD',
28}
29
30class Decoder(srd.Decoder):
af495297 31 api_version = 3
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32 id = 'tlc5620'
33 name = 'TI TLC5620'
34 longname = 'Texas Instruments TLC5620'
35 desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
36 license = 'gplv2+'
37 inputs = ['logic']
38 outputs = ['tlc5620']
6a15597a 39 channels = (
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40 {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
41 {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
da9bcbd9 42 )
6a15597a 43 optional_channels = (
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44 {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
45 {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
da9bcbd9 46 )
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47 options = (
48 {'id': 'vref_a', 'desc': 'Reference voltage DACA (V)', 'default': 3.3},
49 {'id': 'vref_b', 'desc': 'Reference voltage DACB (V)', 'default': 3.3},
50 {'id': 'vref_c', 'desc': 'Reference voltage DACC (V)', 'default': 3.3},
51 {'id': 'vref_d', 'desc': 'Reference voltage DACD (V)', 'default': 3.3},
52 )
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53 annotations = (
54 ('dac-select', 'DAC select'),
55 ('gain', 'Gain'),
56 ('value', 'DAC value'),
57 ('data-latch', 'Data latch point'),
58 ('ldac-fall', 'LDAC falling edge'),
ce0c47f3 59 ('bit', 'Bit'),
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60 ('reg-write', 'Register write'),
61 ('voltage-update', 'Voltage update'),
62 ('voltage-update-all', 'Voltage update (all DACs)'),
a945c536 63 ('invalid-cmd', 'Invalid command'),
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64 )
65 annotation_rows = (
66 ('bits', 'Bits', (5,)),
67 ('fields', 'Fields', (0, 1, 2)),
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68 ('registers', 'Registers', (6, 7)),
69 ('voltage-updates', 'Voltage updates', (8,)),
ce0c47f3 70 ('events', 'Events', (3, 4)),
a945c536 71 ('errors', 'Errors', (9,)),
da9bcbd9 72 )
92d1aba3 73
92b7b49f 74 def __init__(self):
92d1aba3 75 self.bits = []
3992b1e1 76 self.ss_dac_first = None
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77 self.ss_dac = self.es_dac = 0
78 self.ss_gain = self.es_gain = 0
79 self.ss_value = self.es_value = 0
17db4008 80 self.dac_select = self.gain = self.dac_value = None
3992b1e1 81 self.dacval = {'A': '?', 'B': '?', 'C': '?', 'D': '?'}
04c310c8 82 self.gains = {'A': '?', 'B': '?', 'C': '?', 'D': '?'}
92d1aba3 83
8915b346 84 def start(self):
be465111 85 self.out_ann = self.register(srd.OUTPUT_ANN)
92d1aba3 86
92d1aba3 87 def handle_11bits(self):
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88 # Only look at the last 11 bits, the rest is ignored by the TLC5620.
89 if len(self.bits) > 11:
90 self.bits = self.bits[-11:]
91
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92 # If there are less than 11 bits, something is probably wrong.
93 if len(self.bits) < 11:
94 ss, es = self.samplenum, self.samplenum
95 if len(self.bits) >= 2:
96 ss = self.bits[0][1]
97 es = self.bits[-1][1] + (self.bits[1][1] - self.bits[0][1])
98 self.put(ss, es, self.out_ann, [9, ['Command too short']])
99 self.bits = []
100 return False
101
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102 self.ss_dac = self.bits[0][1]
103 self.es_dac = self.ss_gain = self.bits[2][1]
104 self.es_gain = self.ss_value = self.bits[3][1]
105 self.clock_width = self.es_gain - self.ss_gain
106 self.es_value = self.bits[10][1] + self.clock_width # Guessed.
107
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108 if self.ss_dac_first is None:
109 self.ss_dac_first = self.ss_dac
110
ce0c47f3 111 s = ''.join(str(i[0]) for i in self.bits[:2])
7fb4935e 112 self.dac_select = s = dacs[int(s, 2)]
92d1aba3 113 self.put(self.ss_dac, self.es_dac, self.out_ann,
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114 [0, ['DAC select: %s' % s, 'DAC sel: %s' % s,
115 'DAC: %s' % s, 'D: %s' % s, s, s[3]]])
92d1aba3 116
ce0c47f3 117 self.gain = g = 1 + self.bits[2][0]
92d1aba3 118 self.put(self.ss_gain, self.es_gain, self.out_ann,
7fb4935e 119 [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]])
92d1aba3 120
ce0c47f3 121 s = ''.join(str(i[0]) for i in self.bits[3:])
7fb4935e 122 self.dac_value = v = int(s, 2)
92d1aba3 123 self.put(self.ss_value, self.es_value, self.out_ann,
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124 [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,
125 'V: %d' % v, '%d' % v]])
17db4008 126
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127 # Emit an annotation for each bit.
128 for i in range(1, 11):
129 self.put(self.bits[i - 1][1], self.bits[i][1], self.out_ann,
130 [5, [str(self.bits[i - 1][0])]])
131 self.put(self.bits[10][1], self.bits[10][1] + self.clock_width,
132 self.out_ann, [5, [str(self.bits[10][0])]])
133
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134 self.bits = []
135
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136 return True
137
17db4008 138 def handle_falling_edge_load(self):
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139 if not self.handle_11bits():
140 return
7fb4935e 141 s, v, g = self.dac_select, self.dac_value, self.gain
17db4008 142 self.put(self.samplenum, self.samplenum, self.out_ann,
ce0c47f3 143 [3, ['Falling edge on LOAD', 'LOAD fall', 'F']])
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144 vref = self.options['vref_%s' % self.dac_select[3].lower()]
145 v = '%.2fV' % (vref * (v / 256) * self.gain)
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146 if self.ldac == 0:
147 # If LDAC is low, the voltage is set immediately.
148 self.put(self.ss_dac, self.es_value, self.out_ann,
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149 [7, ['Setting %s voltage to %s' % (s, v),
150 '%s=%s' % (s, v)]])
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151 else:
152 # If LDAC is high, the voltage is not set immediately, but rather
153 # stored in a register. When LDAC goes low all four DAC voltages
154 # (DAC A/B/C/D) will be set at the same time.
155 self.put(self.ss_dac, self.es_value, self.out_ann,
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156 [6, ['Setting %s register value to %s' % \
157 (s, v), '%s=%s' % (s, v)]])
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158 # Save the last value the respective DAC was set to.
159 self.dacval[self.dac_select[-1]] = str(self.dac_value)
04c310c8 160 self.gains[self.dac_select[-1]] = self.gain
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161
162 def handle_falling_edge_ldac(self):
163 self.put(self.samplenum, self.samplenum, self.out_ann,
ce0c47f3 164 [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']])
17db4008 165
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166 # Don't emit any annotations if we didn't see any register writes.
167 if self.ss_dac_first is None:
168 return
169
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170 # Calculate voltages based on Vref and the per-DAC gain.
171 dacval = {}
172 for key, val in self.dacval.items():
173 if val == '?':
174 dacval[key] = '?'
175 else:
176 vref = self.options['vref_%s' % key.lower()]
177 v = vref * (int(val) / 256) * self.gains[key]
178 dacval[key] = '%.2fV' % v
179
180 s = ''.join(['DAC%s=%s ' % (d, dacval[d]) for d in 'ABCD']).strip()
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181 self.put(self.ss_dac_first, self.samplenum, self.out_ann,
182 [8, ['Updating voltages: %s' % s, s, s.replace('DAC', '')]])
183 self.ss_dac_first = None
184
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185 def handle_new_dac_bit(self, datapin):
186 self.bits.append([datapin, self.samplenum])
92d1aba3 187
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188 def decode(self):
189 while True:
92d1aba3 190 # DATA is shifted in the DAC on the falling CLK edge (MSB-first).
17db4008 191 # A falling edge of LOAD will latch the data.
92d1aba3 192
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193 # Wait for one (or multiple) of the following conditions:
194 # a) Falling edge on CLK, and/or
195 # b) Falling edge on LOAD, and/or
196 # b) Falling edge on LDAC
197 pins = self.wait([{0: 'f'}, {2: 'f'}, {3: 'f'}])
198 self.ldac = pins[3]
199
200 # Handle those conditions (one or more) that matched this time.
201 if self.matched[0]:
202 self.handle_new_dac_bit(pins[1])
203 if self.matched[1]:
17db4008 204 self.handle_falling_edge_load()
af495297 205 if self.matched[2]:
17db4008 206 self.handle_falling_edge_ldac()