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92d1aba3 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
92d1aba3 | 3 | ## |
ce0c47f3 | 4 | ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de> |
92d1aba3 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
92d1aba3 UH |
21 | import sigrokdecode as srd |
22 | ||
23 | dacs = { | |
24 | 0: 'DACA', | |
25 | 1: 'DACB', | |
26 | 2: 'DACC', | |
27 | 3: 'DACD', | |
28 | } | |
29 | ||
30 | class Decoder(srd.Decoder): | |
12851357 | 31 | api_version = 2 |
92d1aba3 UH |
32 | id = 'tlc5620' |
33 | name = 'TI TLC5620' | |
34 | longname = 'Texas Instruments TLC5620' | |
35 | desc = 'Texas Instruments TLC5620 8-bit quad DAC.' | |
36 | license = 'gplv2+' | |
37 | inputs = ['logic'] | |
38 | outputs = ['tlc5620'] | |
6a15597a | 39 | channels = ( |
92d1aba3 UH |
40 | {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'}, |
41 | {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'}, | |
da9bcbd9 | 42 | ) |
6a15597a | 43 | optional_channels = ( |
92d1aba3 UH |
44 | {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'}, |
45 | {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'}, | |
da9bcbd9 BV |
46 | ) |
47 | annotations = ( | |
48 | ('dac-select', 'DAC select'), | |
49 | ('gain', 'Gain'), | |
50 | ('value', 'DAC value'), | |
51 | ('data-latch', 'Data latch point'), | |
52 | ('ldac-fall', 'LDAC falling edge'), | |
ce0c47f3 | 53 | ('bit', 'Bit'), |
3992b1e1 UH |
54 | ('reg-write', 'Register write'), |
55 | ('voltage-update', 'Voltage update'), | |
56 | ('voltage-update-all', 'Voltage update (all DACs)'), | |
ce0c47f3 UH |
57 | ) |
58 | annotation_rows = ( | |
59 | ('bits', 'Bits', (5,)), | |
60 | ('fields', 'Fields', (0, 1, 2)), | |
3992b1e1 UH |
61 | ('registers', 'Registers', (6, 7)), |
62 | ('voltage-updates', 'Voltage updates', (8,)), | |
ce0c47f3 | 63 | ('events', 'Events', (3, 4)), |
da9bcbd9 | 64 | ) |
92d1aba3 UH |
65 | |
66 | def __init__(self, **kwargs): | |
17db4008 | 67 | self.oldpins = self.oldclk = self.oldload = self.oldldac = None |
92d1aba3 | 68 | self.bits = [] |
3992b1e1 | 69 | self.ss_dac_first = None |
92d1aba3 UH |
70 | self.ss_dac = self.es_dac = 0 |
71 | self.ss_gain = self.es_gain = 0 | |
72 | self.ss_value = self.es_value = 0 | |
17db4008 | 73 | self.dac_select = self.gain = self.dac_value = None |
3992b1e1 | 74 | self.dacval = {'A': '?', 'B': '?', 'C': '?', 'D': '?'} |
92d1aba3 | 75 | |
8915b346 | 76 | def start(self): |
be465111 | 77 | self.out_ann = self.register(srd.OUTPUT_ANN) |
92d1aba3 | 78 | |
92d1aba3 | 79 | def handle_11bits(self): |
e57813d5 UH |
80 | # Only look at the last 11 bits, the rest is ignored by the TLC5620. |
81 | if len(self.bits) > 11: | |
82 | self.bits = self.bits[-11:] | |
83 | ||
84 | self.ss_dac = self.bits[0][1] | |
85 | self.es_dac = self.ss_gain = self.bits[2][1] | |
86 | self.es_gain = self.ss_value = self.bits[3][1] | |
87 | self.clock_width = self.es_gain - self.ss_gain | |
88 | self.es_value = self.bits[10][1] + self.clock_width # Guessed. | |
89 | ||
3992b1e1 UH |
90 | if self.ss_dac_first is None: |
91 | self.ss_dac_first = self.ss_dac | |
92 | ||
ce0c47f3 | 93 | s = ''.join(str(i[0]) for i in self.bits[:2]) |
7fb4935e | 94 | self.dac_select = s = dacs[int(s, 2)] |
92d1aba3 | 95 | self.put(self.ss_dac, self.es_dac, self.out_ann, |
7fb4935e UH |
96 | [0, ['DAC select: %s' % s, 'DAC sel: %s' % s, |
97 | 'DAC: %s' % s, 'D: %s' % s, s, s[3]]]) | |
92d1aba3 | 98 | |
ce0c47f3 | 99 | self.gain = g = 1 + self.bits[2][0] |
92d1aba3 | 100 | self.put(self.ss_gain, self.es_gain, self.out_ann, |
7fb4935e | 101 | [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]]) |
92d1aba3 | 102 | |
ce0c47f3 | 103 | s = ''.join(str(i[0]) for i in self.bits[3:]) |
7fb4935e | 104 | self.dac_value = v = int(s, 2) |
92d1aba3 | 105 | self.put(self.ss_value, self.es_value, self.out_ann, |
7fb4935e UH |
106 | [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v, |
107 | 'V: %d' % v, '%d' % v]]) | |
17db4008 | 108 | |
ce0c47f3 UH |
109 | # Emit an annotation for each bit. |
110 | for i in range(1, 11): | |
111 | self.put(self.bits[i - 1][1], self.bits[i][1], self.out_ann, | |
112 | [5, [str(self.bits[i - 1][0])]]) | |
113 | self.put(self.bits[10][1], self.bits[10][1] + self.clock_width, | |
114 | self.out_ann, [5, [str(self.bits[10][0])]]) | |
115 | ||
e57813d5 UH |
116 | self.bits = [] |
117 | ||
17db4008 | 118 | def handle_falling_edge_load(self): |
e57813d5 | 119 | self.handle_11bits() |
7fb4935e | 120 | s, v, g = self.dac_select, self.dac_value, self.gain |
17db4008 | 121 | self.put(self.samplenum, self.samplenum, self.out_ann, |
ce0c47f3 | 122 | [3, ['Falling edge on LOAD', 'LOAD fall', 'F']]) |
3992b1e1 UH |
123 | if self.ldac == 0: |
124 | # If LDAC is low, the voltage is set immediately. | |
125 | self.put(self.ss_dac, self.es_value, self.out_ann, | |
126 | [7, ['Setting %s voltage to %d (x%d gain)' % (s, v, g), | |
127 | '%s=%d (x%d gain)' % (s, v, g)]]) | |
128 | else: | |
129 | # If LDAC is high, the voltage is not set immediately, but rather | |
130 | # stored in a register. When LDAC goes low all four DAC voltages | |
131 | # (DAC A/B/C/D) will be set at the same time. | |
132 | self.put(self.ss_dac, self.es_value, self.out_ann, | |
133 | [6, ['Setting %s register value to %d (x%d gain)' % \ | |
134 | (s, v, g), '%s=%d (x%d gain)' % (s, v, g)]]) | |
135 | # Save the last value the respective DAC was set to. | |
136 | self.dacval[self.dac_select[-1]] = str(self.dac_value) | |
17db4008 UH |
137 | |
138 | def handle_falling_edge_ldac(self): | |
139 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
ce0c47f3 | 140 | [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']]) |
17db4008 | 141 | |
3992b1e1 UH |
142 | # Don't emit any annotations if we didn't see any register writes. |
143 | if self.ss_dac_first is None: | |
144 | return | |
145 | ||
146 | s = ''.join(['DAC%s=%s ' % (d, self.dacval[d]) for d in 'ABCD']).strip() | |
147 | self.put(self.ss_dac_first, self.samplenum, self.out_ann, | |
148 | [8, ['Updating voltages: %s' % s, s, s.replace('DAC', '')]]) | |
149 | self.ss_dac_first = None | |
150 | ||
17db4008 | 151 | def handle_new_dac_bit(self): |
ce0c47f3 | 152 | self.bits.append([self.datapin, self.samplenum]) |
17db4008 | 153 | |
92d1aba3 UH |
154 | def decode(self, ss, es, data): |
155 | for (self.samplenum, pins) in data: | |
156 | ||
157 | # Ignore identical samples early on (for performance reasons). | |
158 | if self.oldpins == pins: | |
159 | continue | |
17db4008 | 160 | self.oldpins, (clk, self.datapin, load, ldac) = pins, pins |
3992b1e1 | 161 | self.ldac = ldac |
92d1aba3 UH |
162 | |
163 | # DATA is shifted in the DAC on the falling CLK edge (MSB-first). | |
17db4008 | 164 | # A falling edge of LOAD will latch the data. |
92d1aba3 | 165 | |
17db4008 UH |
166 | if self.oldload == 1 and load == 0: |
167 | self.handle_falling_edge_load() | |
168 | if self.oldldac == 1 and ldac == 0: | |
169 | self.handle_falling_edge_ldac() | |
170 | if self.oldclk == 1 and clk == 0: | |
171 | self.handle_new_dac_bit() | |
92d1aba3 UH |
172 | |
173 | self.oldclk = clk | |
17db4008 UH |
174 | self.oldload = load |
175 | self.oldldac = ldac |