]> sigrok.org Git - libsigrokdecode.git/blame - decoders/tca6408a/pd.py
Drop trailing whitespace in various PDs.
[libsigrokdecode.git] / decoders / tca6408a / pd.py
CommitLineData
d4026957 1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
5## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com>
6## Copyright (C) 2014 alberink <alberink@stampfini.org>
7##
8## This program is free software; you can redistribute it and/or modify
9## it under the terms of the GNU General Public License as published by
10## the Free Software Foundation; either version 2 of the License, or
11## (at your option) any later version.
12##
13## This program is distributed in the hope that it will be useful,
14## but WITHOUT ANY WARRANTY; without even the implied warranty of
15## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16## GNU General Public License for more details.
17##
18## You should have received a copy of the GNU General Public License
4539e9ca 19## along with this program; if not, see <http://www.gnu.org/licenses/>.
d4026957 20##
21
22import sigrokdecode as srd
23
24class Decoder(srd.Decoder):
25 api_version = 2
26 id = 'tca6408a'
98c47d11
UH
27 name = 'TI TCA6408A'
28 longname = 'Texas Instruments TCA6408A'
d4026957 29 desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.'
30 license = 'gplv2+'
31 inputs = ['i2c']
32 outputs = ['tca6408a']
33 annotations = (
34 ('register', 'Register type'),
35 ('value', 'Register value'),
36 ('warnings', 'Warning messages'),
37 )
38 annotation_rows = (
39 ('regs', 'Registers', (0, 1)),
40 ('warnings', 'Warnings', (2,)),
41 )
42
92b7b49f 43 def __init__(self):
d4026957 44 self.state = 'IDLE'
45 self.chip = -1
46
47 def start(self):
48 self.out_ann = self.register(srd.OUTPUT_ANN)
49
50 def putx(self, data):
51 self.put(self.ss, self.es, self.out_ann, data)
52
53 def handle_reg_0x00(self, b):
54 self.putx([1, ['State of inputs: %02X' % b]])
55
56 def handle_reg_0x01(self, b):
57 self.putx([1, ['Outputs set: %02X' % b ]])
58
59 def handle_reg_0x02(self, b):
60 self.putx([1, ['Polarity inverted: %02X' % b]])
61
62 def handle_reg_0x03(self, b):
63 self.putx([1, ['Configuration: %02X' % b]])
64
65 def handle_write_reg(self, b):
66 if b == 0:
67 self.putx([0, ['Input port', 'In', 'I']])
68 elif b == 1:
69 self.putx([0, ['Output port', 'Out', 'O']])
70 elif b == 2:
71 self.putx([0, ['Polarity inversion register', 'Pol', 'P']])
72 elif b == 3:
73 self.putx([0, ['Configuration register', 'Conf', 'C']])
74
75 def check_correct_chip(self, addr):
76 if addr not in (0x20, 0x21):
77 self.putx([2, ['Warning: I²C slave 0x%02X not a TCA6408A '
78 'compatible chip.' % addr]])
79 self.state = 'IDLE'
80
81 def decode(self, ss, es, data):
82 cmd, databyte = data
83
84 # Store the start/end samples of this I²C packet.
85 self.ss, self.es = ss, es
86
87 # State machine.
88 if self.state == 'IDLE':
89 # Wait for an I²C START condition.
90 if cmd != 'START':
91 return
92 self.state = 'GET SLAVE ADDR'
d4026957 93 elif self.state == 'GET SLAVE ADDR':
18101a31 94 self.chip = databyte
d4026957 95 self.state = 'GET REG ADDR'
96 elif self.state == 'GET REG ADDR':
97 # Wait for a data write (master selects the slave register).
98 if cmd in ('ADDRESS READ', 'ADDRESS WRITE'):
99 self.check_correct_chip(databyte)
100 if cmd != 'DATA WRITE':
101 return
102 self.reg = databyte
103 self.handle_write_reg(self.reg)
104 self.state = 'WRITE IO REGS'
105 elif self.state == 'WRITE IO REGS':
106 # If we see a Repeated Start here, the master wants to read.
107 if cmd == 'START REPEAT':
108 self.state = 'READ IO REGS'
109 return
110 # Otherwise: Get data bytes until a STOP condition occurs.
111 if cmd == 'DATA WRITE':
112 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
113 handle_reg(databyte)
114 elif cmd == 'STOP':
115 self.state = 'IDLE'
116 self.chip = -1
117 elif self.state == 'READ IO REGS':
118 # Wait for an address read operation.
119 if cmd == 'ADDRESS READ':
120 self.state = 'READ IO REGS2'
121 self.chip = databyte
122 return
123 elif self.state == 'READ IO REGS2':
124 if cmd == 'DATA READ':
125 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
126 handle_reg(databyte)
127 elif cmd == 'STOP':
128 self.state = 'IDLE'