]> sigrok.org Git - libsigrokdecode.git/blame - decoders/srd_usb.py
srd: Decoders: Cosmetics and whitespace fixes.
[libsigrokdecode.git] / decoders / srd_usb.py
CommitLineData
03325c23
GM
1##
2## This file is part of the sigrok project.
3##
4## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
9611dc5f 21#
03325c23 22# USB Full-speed protocol decoder
9611dc5f
UH
23#
24# Full-speed USB signalling consists of two signal lines, both driven at 3.3V
25# logic levels. The signals are DP (D+) and DM (D-), and normally operate in
26# differential mode.
03325c23 27# The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.
9611dc5f 28# A state SE0 is defined where DP=DM=0. This common mode signal is used to
03325c23 29# signal a reset or end of packet.
9611dc5f
UH
30#
31# Data transmitted on the USB is encoded with NRZI. A transition from J to K
32# or vice-versa indicates a logic 0, while no transition indicates a logic 1.
33# If 6 ones are transmitted consecutively, a zero is inserted to force a
34# transition. This is known as bit stuffing. Data is transferred at a rate
35# of 12Mbit/s. The SE0 transmitted to signal an end-of-packet is two bit
03325c23 36# intervals long.
9611dc5f
UH
37#
38# Details:
39# https://en.wikipedia.org/wiki/USB
40# http://www.usb.org/developers/docs/
41#
03325c23 42
677d597b 43import sigrokdecode as srd
03325c23 44
9611dc5f 45# States
03325c23
GM
46SE0, J, K, SE1 = 0, 1, 2, 3
47syms = {
c66baa8c
UH
48 (0, 0): SE0,
49 (1, 0): J,
50 (0, 1): K,
51 (1, 1): SE1,
03325c23
GM
52}
53
54def bitstr_to_num(bitstr):
eb7082c9
UH
55 if not bitstr:
56 return 0
03325c23
GM
57 l = list(bitstr)
58 l.reverse()
59 return int(''.join(l), 2)
60
61def packet_decode(packet):
9611dc5f 62 pids = {
eb7082c9
UH
63 '10000111': 'OUT', # Tokens
64 '10010110': 'IN',
65 '10100101': 'SOF',
66 '10110100': 'SETUP',
67 '11000011': 'DATA0', # Data
68 '11010010': 'DATA1',
69 '01001011': 'ACK', # Handshake
70 '01011010': 'NAK',
71 '01111000': 'STALL',
72 '01101001': 'NYET',
03325c23
GM
73 }
74
75 sync = packet[:8]
76 pid = packet[8:16]
77 pid = pids.get(pid, pid)
eb7082c9 78
9611dc5f 79 # Remove CRC.
03325c23
GM
80 if pid in ('OUT', 'IN', 'SOF', 'SETUP'):
81 data = packet[16:-5]
82 if pid == 'SOF':
83 data = str(bitstr_to_num(data))
84 else:
85 dev = bitstr_to_num(data[:7])
86 ep = bitstr_to_num(data[7:])
eb7082c9 87 data = 'DEV %d EP %d' % (dev, ep)
03325c23
GM
88
89 elif pid in ('DATA0', 'DATA1'):
90 data = packet[16:-16]
eb7082c9 91 tmp = ''
03325c23 92 while data:
eb7082c9 93 tmp += '%02X ' % bitstr_to_num(data[:8])
03325c23
GM
94 data = data[8:]
95 data = tmp
96 else:
97 data = packet[16:]
98
eb7082c9
UH
99 if sync != '00000001':
100 return 'SYNC INVALID!'
9611dc5f 101
03325c23
GM
102 return pid + ' ' + data
103
677d597b 104class Decoder(srd.Decoder):
67e847fd 105 id = 'usb'
03325c23
GM
106 name = 'USB'
107 desc = 'Universal Serial Bus'
108 longname = '...longname...'
109 longdesc = '...longdesc...'
110 author = 'Gareth McMullin'
111 email = 'gareth@blacksphere.co.nz'
112 license = 'gplv2+'
113 inputs = ['logic']
114 outputs = ['usb']
ea42f53e
UH
115 probes = [
116 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
117 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
118 ]
03325c23
GM
119 options = {}
120
121 def __init__(self):
d0e93c76 122 pass
03325c23
GM
123
124 def start(self, metadata):
03325c23 125 self.rate = metadata['samplerate']
56202222
UH
126 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb')
127 self.out_ann = self.add(srd.OUTPUT_ANN, 'usb')
03325c23 128 if self.rate < 48000000:
eb7082c9 129 raise Exception('Sample rate not sufficient for USB decoding')
9611dc5f 130 # Initialise decoder state.
03325c23
GM
131 self.sym = J
132 self.scount = 0
133 self.packet = ''
134
b327337f
UH
135 def decode(self, timeoffset, duration, data):
136 out = []
137
ea42f53e
UH
138 # FIXME
139 for (samplenum, (dp, dm, x, y, z, a)) in data:
03325c23
GM
140
141 self.scount += 1
142
ea42f53e 143 sym = syms[dp, dm]
03325c23
GM
144 if sym == self.sym:
145 continue
146
147 if self.scount == 1:
9611dc5f
UH
148 # We ignore single sample width pulses.
149 # I sometimes get these with the OLS.
03325c23
GM
150 self.sym = sym
151 self.scount = 0
152 continue
153
9611dc5f 154 # How many bits since the last transition?
03325c23 155 if self.packet or self.sym != J:
b327337f 156 bitcount = int((self.scount - 1) * 12000000 / self.rate)
03325c23
GM
157 else:
158 bitcount = 0
159
160 if self.sym == SE0:
161 if bitcount == 1:
9611dc5f 162 # End-Of-Packet (EOP)
eb7082c9
UH
163 out += [{'type': 'usb', 'data': self.packet,
164 'display': packet_decode(self.packet)}]
03325c23 165 else:
9611dc5f 166 # Longer than EOP, assume reset.
eb7082c9 167 out += [{'type': 'usb', 'display': 'RESET'}]
03325c23
GM
168 self.scount = 0
169 self.sym = sym
170 self.packet = ''
171 continue
172
173 # Add bits to the packet string.
174 self.packet += '1' * bitcount
9611dc5f 175 # Handle bit stuffing.
03325c23
GM
176 if bitcount < 6 and sym != SE0:
177 self.packet += '0'
178 elif bitcount > 6:
eb7082c9 179 out += [{'type': 'usb', 'display': 'BIT STUFF ERROR'}]
9611dc5f 180
03325c23
GM
181 self.scount = 0
182 self.sym = sym
183
b327337f 184 if out != []:
c9b24fc3
UH
185 # self.put(0, 0, self.out_proto, out_proto)
186 self.put(0, 0, self.out_ann, out)
b327337f 187