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spiflash: Add lists.py and a 'chips' PD option.
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1b1c914f 1##
50bd5d25 2## This file is part of the libsigrokdecode project.
1b1c914f 3##
3ca1f1b3 4## Copyright (C) 2011-2015 Uwe Hermann <uwe@hermann-uwe.de>
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5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
677d597b 21import sigrokdecode as srd
c2446117 22from .lists import *
1b1c914f 23
9389f2c1 24def cmd_annotation_classes():
da9bcbd9 25 return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()])
9389f2c1 26
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27def decode_status_reg(data):
28 # TODO: Additional per-bit(s) self.put() calls with correct start/end.
29
30 # Bits[0:0]: WIP (write in progress)
31 s = 'W' if (data & (1 << 0)) else 'No w'
32 ret = '%srite operation in progress.\n' % s
33
34 # Bits[1:1]: WEL (write enable latch)
35 s = '' if (data & (1 << 1)) else 'not '
36 ret += 'Internal write enable latch is %sset.\n' % s
37
38 # Bits[5:2]: Block protect bits
39 # TODO: More detailed decoding (chip-dependent).
40 ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
41
42 # Bits[6:6]: Continuously program mode (CP mode)
43 s = '' if (data & (1 << 6)) else 'not '
44 ret += 'Device is %sin continuously program mode (CP mode).\n' % s
45
46 # Bits[7:7]: SRWD (status register write disable)
cd287c56 47 s = 'not ' if (data & (1 << 7)) else ''
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48 ret += 'Status register writes are %sallowed.\n' % s
49
50 return ret
51
677d597b 52class Decoder(srd.Decoder):
12851357 53 api_version = 2
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54 id = 'spiflash'
55 name = 'SPI flash'
56 longname = 'SPI flash chips'
57 desc = 'xx25 series SPI (NOR) flash chip protocol.'
1b1c914f 58 license = 'gplv2+'
4e4f8527 59 inputs = ['logic']
3ca1f1b3 60 outputs = ['spiflash']
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61 annotations = cmd_annotation_classes() + (
62 ('bits', 'Bits'),
63 ('bits2', 'Bits2'),
64 ('warnings', 'Warnings'),
65 )
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66 annotation_rows = (
67 ('bits', 'Bits', (24, 25)),
68 ('commands', 'Commands', tuple(range(23 + 1))),
69 ('warnings', 'Warnings', (26,)),
70 )
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71 options = (
72 {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0],
73 'values': tuple(chips.keys())},
74 )
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75
76 def __init__(self, **kwargs):
4772a846 77 self.state = None
781ef945 78 self.cmdstate = 1
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79 self.addr = 0
80 self.data = []
1b1c914f 81
8915b346 82 def start(self):
be465111 83 self.out_ann = self.register(srd.OUTPUT_ANN)
c2446117 84 self.chip = chips[self.options['chip']]
1b1c914f 85
385508e9 86 def putx(self, data):
ee3e279c 87 # Simplification, most annotations span exactly one SPI byte/packet.
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88 self.put(self.ss, self.es, self.out_ann, data)
89
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90 def putb(self, data):
91 self.put(self.block_ss, self.block_es, self.out_ann, data)
92
9b4d8a57 93 def handle_wren(self, mosi, miso):
781ef945 94 self.putx([0, ['Command: %s' % cmds[self.state][1]]])
4772a846 95 self.state = None
1b1c914f 96
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97 def handle_wrdi(self, mosi, miso):
98 pass # TODO
99
1b1c914f 100 # TODO: Check/display device ID / name
9b4d8a57 101 def handle_rdid(self, mosi, miso):
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102 if self.cmdstate == 1:
103 # Byte 1: Master sends command ID.
486b19ce 104 self.ss_block = self.ss
9389f2c1 105 self.putx([2, ['Command: %s' % cmds[self.state][1]]])
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106 elif self.cmdstate == 2:
107 # Byte 2: Slave sends the JEDEC manufacturer ID.
9389f2c1 108 self.putx([2, ['Manufacturer ID: 0x%02x' % miso]])
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109 elif self.cmdstate == 3:
110 # Byte 3: Slave sends the memory type (0x20 for this chip).
9389f2c1 111 self.putx([2, ['Memory type: 0x%02x' % miso]])
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112 elif self.cmdstate == 4:
113 # Byte 4: Slave sends the device ID.
9b4d8a57 114 self.device_id = miso
9389f2c1 115 self.putx([2, ['Device ID: 0x%02x' % miso]])
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116
117 if self.cmdstate == 4:
118 # TODO: Check self.device_id is valid & exists in device_names.
119 # TODO: Same device ID? Check!
9b4d8a57 120 d = 'Device: Macronix %s' % device_name[self.device_id]
486b19ce 121 self.put(self.ss_block, self.es, self.out_ann, [0, [d]])
4772a846 122 self.state = None
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123 else:
124 self.cmdstate += 1
125
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126 def handle_rdsr(self, mosi, miso):
127 # Read status register: Master asserts CS#, sends RDSR command,
128 # reads status register byte. If CS# is kept asserted, the status
129 # register can be read continuously / multiple times in a row.
130 # When done, the master de-asserts CS# again.
131 if self.cmdstate == 1:
132 # Byte 1: Master sends command ID.
9389f2c1 133 self.putx([3, ['Command: %s' % cmds[self.state][1]]])
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134 elif self.cmdstate >= 2:
135 # Bytes 2-x: Slave sends status register as long as master clocks.
136 if self.cmdstate <= 3: # TODO: While CS# asserted.
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137 self.putx([24, ['Status register: 0x%02x' % miso]])
138 self.putx([25, [decode_status_reg(miso)]])
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139
140 if self.cmdstate == 3: # TODO: If CS# got de-asserted.
141 self.state = None
142 return
143
144 self.cmdstate += 1
145
146 def handle_wrsr(self, mosi, miso):
147 pass # TODO
148
149 def handle_read(self, mosi, miso):
150 # Read data bytes: Master asserts CS#, sends READ command, sends
151 # 3-byte address, reads >= 1 data bytes, de-asserts CS#.
152 if self.cmdstate == 1:
153 # Byte 1: Master sends command ID.
9389f2c1 154 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
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155 elif self.cmdstate in (2, 3, 4):
156 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
157 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
158 # self.putx([0, ['Read address, byte %d: 0x%02x' % \
159 # (4 - self.cmdstate, mosi)]])
160 if self.cmdstate == 4:
9389f2c1 161 self.putx([24, ['Read address: 0x%06x' % self.addr]])
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162 self.addr = 0
163 elif self.cmdstate >= 5:
164 # Bytes 5-x: Master reads data bytes (until CS# de-asserted).
165 # TODO: For now we hardcode 256 bytes per READ command.
166 if self.cmdstate <= 256 + 4: # TODO: While CS# asserted.
167 self.data.append(miso)
168 # self.putx([0, ['New read byte: 0x%02x' % miso]])
169
170 if self.cmdstate == 256 + 4: # TODO: If CS# got de-asserted.
171 # s = ', '.join(map(hex, self.data))
172 s = ''.join(map(chr, self.data))
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173 self.putx([24, ['Read data']])
174 self.putx([25, ['Read data: %s' % s]])
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175 self.data = []
176 self.state = None
177 return
178
179 self.cmdstate += 1
180
181 def handle_fast_read(self, mosi, miso):
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182 # Fast read: Master asserts CS#, sends FAST READ command, sends
183 # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#.
184 if self.cmdstate == 1:
185 # Byte 1: Master sends command ID.
186 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
187 elif self.cmdstate in (2, 3, 4):
188 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
189 self.putx([24, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]])
190 if self.cmdstate == 2:
191 self.block_ss = self.ss
192 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
193 elif self.cmdstate == 5:
194 self.putx([24, ['Dummy byte: 0x%02x' % mosi]])
195 self.block_es = self.es
196 self.putb([5, ['Read address: 0x%06x' % self.addr]])
197 self.addr = 0
198 elif self.cmdstate >= 6:
199 # Bytes 6-x: Master reads data bytes (until CS# de-asserted).
200 # TODO: For now we hardcode 32 bytes per FAST READ command.
201 if self.cmdstate == 6:
202 self.block_ss = self.ss
203 if self.cmdstate <= 32 + 5: # TODO: While CS# asserted.
204 self.data.append(miso)
205 if self.cmdstate == 32 + 5: # TODO: If CS# got de-asserted.
206 self.block_es = self.es
207 s = ' '.join([hex(b)[2:] for b in self.data])
208 self.putb([25, ['Read data: %s' % s]])
209 self.data = []
210 self.state = None
211 return
212
213 self.cmdstate += 1
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214
215 def handle_2read(self, mosi, miso):
216 pass # TODO
217
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218 # TODO: Warn/abort if we don't see the necessary amount of bytes.
219 # TODO: Warn if WREN was not seen before.
9b4d8a57 220 def handle_se(self, mosi, miso):
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221 if self.cmdstate == 1:
222 # Byte 1: Master sends command ID.
223 self.addr = 0
486b19ce 224 self.ss_block = self.ss
9389f2c1 225 self.putx([8, ['Command: %s' % cmds[self.state][1]]])
1b1c914f 226 elif self.cmdstate in (2, 3, 4):
868fd207 227 # Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
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228 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
229 # self.putx([0, ['Sector address, byte %d: 0x%02x' % \
230 # (4 - self.cmdstate, mosi)]])
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231
232 if self.cmdstate == 4:
87e574b7 233 d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
486b19ce 234 self.put(self.ss_block, self.es, self.out_ann, [24, [d]])
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235 # TODO: Max. size depends on chip, check that too if possible.
236 if self.addr % 4096 != 0:
237 # Sector addresses must be 4K-aligned (same for all 3 chips).
173c919c 238 d = 'Warning: Invalid sector address!'
486b19ce 239 self.put(self.ss_block, self.es, self.out_ann, [101, [d]])
4772a846 240 self.state = None
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241 else:
242 self.cmdstate += 1
243
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244 def handle_be(self, mosi, miso):
245 pass # TODO
246
247 def handle_ce(self, mosi, miso):
248 pass # TODO
249
250 def handle_ce2(self, mosi, miso):
251 pass # TODO
252
253 def handle_pp(self, mosi, miso):
254 # Page program: Master asserts CS#, sends PP command, sends 3-byte
255 # page address, sends >= 1 data bytes, de-asserts CS#.
256 if self.cmdstate == 1:
257 # Byte 1: Master sends command ID.
9389f2c1 258 self.putx([12, ['Command: %s' % cmds[self.state][1]]])
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259 elif self.cmdstate in (2, 3, 4):
260 # Bytes 2/3/4: Master sends page address (24bits, MSB-first).
261 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
262 # self.putx([0, ['Page address, byte %d: 0x%02x' % \
263 # (4 - self.cmdstate, mosi)]])
264 if self.cmdstate == 4:
9389f2c1 265 self.putx([24, ['Page address: 0x%06x' % self.addr]])
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266 self.addr = 0
267 elif self.cmdstate >= 5:
268 # Bytes 5-x: Master sends data bytes (until CS# de-asserted).
269 # TODO: For now we hardcode 256 bytes per page / PP command.
270 if self.cmdstate <= 256 + 4: # TODO: While CS# asserted.
271 self.data.append(mosi)
272 # self.putx([0, ['New data byte: 0x%02x' % mosi]])
273
274 if self.cmdstate == 256 + 4: # TODO: If CS# got de-asserted.
275 # s = ', '.join(map(hex, self.data))
276 s = ''.join(map(chr, self.data))
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277 self.putx([24, ['Page data']])
278 self.putx([25, ['Page data: %s' % s]])
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279 self.data = []
280 self.state = None
281 return
282
283 self.cmdstate += 1
284
285 def handle_cp(self, mosi, miso):
286 pass # TODO
287
288 def handle_dp(self, mosi, miso):
289 pass # TODO
290
291 def handle_rdp_res(self, mosi, miso):
292 pass # TODO
293
9b4d8a57 294 def handle_rems(self, mosi, miso):
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295 if self.cmdstate == 1:
296 # Byte 1: Master sends command ID.
486b19ce 297 self.ss_block = self.ss
9389f2c1 298 self.putx([16, ['Command: %s' % cmds[self.state][1]]])
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299 elif self.cmdstate in (2, 3):
300 # Bytes 2/3: Master sends two dummy bytes.
301 # TODO: Check dummy bytes? Check reply from device?
9389f2c1 302 self.putx([24, ['Dummy byte: %s' % mosi]])
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303 elif self.cmdstate == 4:
304 # Byte 4: Master sends 0x00 or 0x01.
305 # 0x00: Master wants manufacturer ID as first reply byte.
306 # 0x01: Master wants device ID as first reply byte.
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307 self.manufacturer_id_first = True if (mosi == 0x00) else False
308 d = 'manufacturer' if (mosi == 0x00) else 'device'
9389f2c1 309 self.putx([24, ['Master wants %s ID first' % d]])
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310 elif self.cmdstate == 5:
311 # Byte 5: Slave sends manufacturer ID (or device ID).
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312 self.ids = [miso]
313 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
9389f2c1 314 self.putx([24, ['%s ID' % d]])
9b4d8a57 315 elif self.cmdstate == 6:
1b1c914f 316 # Byte 6: Slave sends device ID (or manufacturer ID).
7f7ea759 317 self.ids.append(miso)
9b4d8a57 318 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
9389f2c1 319 self.putx([24, ['%s ID' % d]])
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320
321 if self.cmdstate == 6:
1b1c914f 322 id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
9389f2c1 323 self.putx([24, ['Device: Macronix %s' % device_name[id]]])
4772a846 324 self.state = None
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325 else:
326 self.cmdstate += 1
327
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328 def handle_rems2(self, mosi, miso):
329 pass # TODO
e4022299 330
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331 def handle_enso(self, mosi, miso):
332 pass # TODO
e4022299 333
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334 def handle_exso(self, mosi, miso):
335 pass # TODO
e4022299 336
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337 def handle_rdscur(self, mosi, miso):
338 pass # TODO
e4022299 339
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340 def handle_wrscur(self, mosi, miso):
341 pass # TODO
e4022299 342
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343 def handle_esry(self, mosi, miso):
344 pass # TODO
1b1c914f 345
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346 def handle_dsry(self, mosi, miso):
347 pass # TODO
5ebb76fe 348
2b9837d9 349 def decode(self, ss, es, data):
1b1c914f 350
9b4d8a57 351 ptype, mosi, miso = data
1b1c914f 352
e4022299 353 # if ptype == 'DATA':
781ef945 354 # self.putx([0, ['MOSI: 0x%02x, MISO: 0x%02x' % (mosi, miso)]])
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355
356 # if ptype == 'CS-CHANGE':
357 # if mosi == 1 and miso == 0:
781ef945 358 # self.putx([0, ['Asserting CS#']])
e4022299 359 # elif mosi == 0 and miso == 1:
781ef945 360 # self.putx([0, ['De-asserting CS#']])
e4022299 361
3e3c0330 362 if ptype != 'DATA':
9b4d8a57 363 return
1b1c914f 364
e4022299 365 self.ss, self.es = ss, es
1b1c914f 366
9b4d8a57 367 # If we encountered a known chip command, enter the resp. state.
35b380b1 368 if self.state is None:
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369 self.state = mosi
370 self.cmdstate = 1
1b1c914f 371
9b4d8a57 372 # Handle commands.
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373 if self.state in cmds:
374 s = 'handle_%s' % cmds[self.state][0].lower().replace('/', '_')
375 handle_reg = getattr(self, s)
4772a846 376 handle_reg(mosi, miso)
9b4d8a57 377 else:
9389f2c1 378 self.putx([24, ['Unknown command: 0x%02x' % mosi]])
4772a846 379 self.state = None