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6eb87578 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
6eb87578 GM |
3 | ## |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
3eda7779 | 5 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
6eb87578 GM |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
ad2dc0de | 21 | |
677d597b | 22 | import sigrokdecode as srd |
67e847fd | 23 | |
0702e0cf UH |
24 | ''' |
25 | Protocol output format: | |
26 | ||
27 | SPI packet: | |
28 | [<cmd>, <data1>, <data2>] | |
29 | ||
30 | Commands: | |
31 | - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data. | |
32 | The data is _usually_ 8 bits (but can also be fewer or more bits). | |
33 | Both data items are Python numbers, not strings. | |
34 | - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value. | |
35 | Both data items are Python numbers (0/1), not strings. | |
36 | ||
37 | Examples: | |
38 | ['CS-CHANGE', 1, 0] | |
39 | ['DATA', 0xff, 0x3a] | |
40 | ['DATA', 0x65, 0x00] | |
41 | ['CS-CHANGE', 0, 1] | |
42 | ''' | |
43 | ||
8a7ce2a3 | 44 | # Key: (CPOL, CPHA). Value: SPI mode. |
94bbdb9a UH |
45 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. |
46 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
c94c8c91 UH |
47 | spi_mode = { |
48 | (0, 0): 0, # Mode 0 | |
49 | (0, 1): 1, # Mode 1 | |
50 | (1, 0): 2, # Mode 2 | |
51 | (1, 1): 3, # Mode 3 | |
52 | } | |
53 | ||
677d597b | 54 | class Decoder(srd.Decoder): |
a2c2afd9 | 55 | api_version = 1 |
67e847fd | 56 | id = 'spi' |
2b7d0e2b | 57 | name = 'SPI' |
3d3da57d | 58 | longname = 'Serial Peripheral Interface' |
a465436e | 59 | desc = 'Full-duplex, synchronous, serial bus.' |
6eb87578 GM |
60 | license = 'gplv2+' |
61 | inputs = ['logic'] | |
62 | outputs = ['spi'] | |
6b5b91d2 | 63 | probes = [ |
4e570fa9 UH |
64 | {'id': 'miso', 'name': 'MISO', |
65 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
decde15e UH |
66 | {'id': 'mosi', 'name': 'MOSI', |
67 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
6b5b91d2 UH |
68 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, |
69 | ] | |
efa64173 UH |
70 | optional_probes = [ |
71 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, | |
72 | ] | |
238b4080 | 73 | options = { |
94bbdb9a UH |
74 | 'cs_polarity': ['CS# polarity', 'active-low'], |
75 | 'cpol': ['Clock polarity', 0], | |
76 | 'cpha': ['Clock phase', 0], | |
77 | 'bitorder': ['Bit order within the SPI data', 'msb-first'], | |
c94c8c91 | 78 | 'wordsize': ['Word size of SPI data', 8], # 1-64? |
3eda7779 | 79 | 'format': ['Data format', 'hex'], |
238b4080 | 80 | } |
b1bb5eed | 81 | annotations = [ |
9f2f42c0 UH |
82 | ['miso-mosi-data', 'MISO/MOSI SPI data'], |
83 | ['miso-data', 'MISO SPI data'], | |
84 | ['mosi-data', 'MOSI SPI data'], | |
85 | ['warnings', 'Human-readable warnings'], | |
b1bb5eed | 86 | ] |
6eb87578 | 87 | |
3643fc3f | 88 | def __init__(self): |
8a3c8792 | 89 | self.samplerate = None |
c66baa8c | 90 | self.oldsck = 1 |
a10bfc48 | 91 | self.bitcount = 0 |
4917bb31 | 92 | self.mosidata = 0 |
d6bace96 | 93 | self.misodata = 0 |
ec0afe27 | 94 | self.startsample = -1 |
d6bace96 | 95 | self.samplenum = -1 |
01329e88 | 96 | self.cs_was_deasserted_during_data_word = 0 |
3e3c0330 | 97 | self.oldcs = -1 |
2fcd7c22 | 98 | self.oldpins = None |
191ec8c5 | 99 | self.state = 'IDLE' |
6eb87578 | 100 | |
8a3c8792 BV |
101 | def metadata(self, key, value): |
102 | if key == srd.SRD_CONF_SAMPLERATE: | |
103 | self.samplerate = value | |
104 | ||
8915b346 | 105 | def start(self): |
be465111 BV |
106 | self.out_proto = self.register(srd.OUTPUT_PYTHON) |
107 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
8a3c8792 BV |
108 | self.out_bitrate = self.register(srd.OUTPUT_META, |
109 | meta=(int, 'Bitrate', 'Bitrate during transfers')) | |
3643fc3f | 110 | |
ec0afe27 UH |
111 | def putpw(self, data): |
112 | self.put(self.startsample, self.samplenum, self.out_proto, data) | |
113 | ||
114 | def putw(self, data): | |
115 | self.put(self.startsample, self.samplenum, self.out_ann, data) | |
116 | ||
191ec8c5 UH |
117 | def handle_bit(self, miso, mosi, sck, cs): |
118 | # If this is the first bit, save its sample number. | |
119 | if self.bitcount == 0: | |
120 | self.startsample = self.samplenum | |
efa64173 UH |
121 | if self.have_cs: |
122 | active_low = (self.options['cs_polarity'] == 'active-low') | |
123 | deasserted = cs if active_low else not cs | |
124 | if deasserted: | |
125 | self.cs_was_deasserted_during_data_word = 1 | |
2fcd7c22 | 126 | |
191ec8c5 | 127 | ws = self.options['wordsize'] |
d6bace96 | 128 | |
191ec8c5 UH |
129 | # Receive MOSI bit into our shift register. |
130 | if self.options['bitorder'] == 'msb-first': | |
131 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
132 | else: | |
133 | self.mosidata |= mosi << self.bitcount | |
3e3c0330 | 134 | |
191ec8c5 UH |
135 | # Receive MISO bit into our shift register. |
136 | if self.options['bitorder'] == 'msb-first': | |
137 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
138 | else: | |
139 | self.misodata |= miso << self.bitcount | |
c94c8c91 | 140 | |
191ec8c5 | 141 | self.bitcount += 1 |
1ea831e9 | 142 | |
191ec8c5 UH |
143 | # Continue to receive if not enough bits were received, yet. |
144 | if self.bitcount != ws: | |
145 | return | |
b1bb5eed | 146 | |
8a3c8792 | 147 | # Pass MOSI and MISO to the next PD up the stack |
191ec8c5 | 148 | self.putpw(['DATA', self.mosidata, self.misodata]) |
8a3c8792 BV |
149 | |
150 | # Annotations | |
191ec8c5 UH |
151 | self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) |
152 | self.putw([1, ['%02X' % self.misodata]]) | |
153 | self.putw([2, ['%02X' % self.mosidata]]) | |
b1bb5eed | 154 | |
8a3c8792 BV |
155 | # Meta bitrate |
156 | elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1) | |
157 | bitrate = int(1 / elapsed * self.options['wordsize']) | |
158 | self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) | |
159 | ||
191ec8c5 UH |
160 | if self.cs_was_deasserted_during_data_word: |
161 | self.putw([3, ['CS# was deasserted during this data word!']]) | |
162 | ||
163 | # Reset decoder state. | |
efa64173 | 164 | self.mosidata = self.misodata = self.bitcount = 0 |
191ec8c5 | 165 | |
191ec8c5 | 166 | def find_clk_edge(self, miso, mosi, sck, cs): |
efa64173 | 167 | if self.have_cs and self.oldcs != cs: |
191ec8c5 UH |
168 | # Send all CS# pin value changes. |
169 | self.put(self.samplenum, self.samplenum, self.out_proto, | |
170 | ['CS-CHANGE', self.oldcs, cs]) | |
171 | self.oldcs = cs | |
efa64173 UH |
172 | # Reset decoder state when CS# changes (and the CS# pin is used). |
173 | self.mosidata = self.misodata = self.bitcount= 0 | |
191ec8c5 UH |
174 | |
175 | # Ignore sample if the clock pin hasn't changed. | |
176 | if sck == self.oldsck: | |
177 | return | |
b1bb5eed | 178 | |
191ec8c5 | 179 | self.oldsck = sck |
b1bb5eed | 180 | |
191ec8c5 UH |
181 | # Sample data on rising/falling clock edge (depends on mode). |
182 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
183 | if mode == 0 and sck == 0: # Sample on rising clock edge | |
184 | return | |
185 | elif mode == 1 and sck == 1: # Sample on falling clock edge | |
186 | return | |
187 | elif mode == 2 and sck == 1: # Sample on falling clock edge | |
188 | return | |
189 | elif mode == 3 and sck == 0: # Sample on rising clock edge | |
190 | return | |
191 | ||
192 | # Found the correct clock edge, now get the SPI bit(s). | |
193 | self.handle_bit(miso, mosi, sck, cs) | |
194 | ||
195 | def decode(self, ss, es, data): | |
8a3c8792 BV |
196 | if self.samplerate is None: |
197 | raise Exception("Cannot decode without samplerate.") | |
191ec8c5 UH |
198 | # TODO: Either MISO or MOSI could be optional. CS# is optional. |
199 | for (self.samplenum, pins) in data: | |
01329e88 | 200 | |
191ec8c5 UH |
201 | # Ignore identical samples early on (for performance reasons). |
202 | if self.oldpins == pins: | |
203 | continue | |
204 | self.oldpins, (miso, mosi, sck, cs) = pins, pins | |
efa64173 | 205 | self.have_cs = (cs in (0, 1)) |
b1bb5eed | 206 | |
191ec8c5 UH |
207 | # State machine. |
208 | if self.state == 'IDLE': | |
209 | self.find_clk_edge(miso, mosi, sck, cs) | |
210 | else: | |
211 | raise Exception('Invalid state: %s' % self.state) | |
ad2dc0de | 212 |