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1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | class Decoder(srd.Decoder): | |
24 | id = 'spi' | |
25 | name = 'SPI' | |
26 | longname = 'Serial Peripheral Interface (SPI) bus' | |
27 | desc = '...desc...' | |
28 | longdesc = '...longdesc...' | |
29 | author = 'Gareth McMullin' | |
30 | email = 'gareth@blacksphere.co.nz' | |
31 | license = 'gplv2+' | |
32 | inputs = ['logic'] | |
33 | outputs = ['spi'] | |
34 | probes = [ | |
35 | {'id': 'mosi', 'name': 'MOSI', | |
36 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
37 | {'id': 'miso', 'name': 'MISO', | |
38 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
39 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, | |
40 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, | |
41 | ] | |
42 | options = {} | |
43 | annotations = [ | |
44 | ['TODO', 'TODO'], | |
45 | ] | |
46 | ||
47 | def __init__(self): | |
48 | self.oldsck = 1 | |
49 | self.bitcount = 0 | |
50 | self.mosidata = 0 | |
51 | self.bytesreceived = 0 | |
52 | ||
53 | def start(self, metadata): | |
54 | # self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') | |
55 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') | |
56 | ||
57 | def report(self): | |
58 | return 'SPI: %d bytes received' % self.bytesreceived | |
59 | ||
60 | def decode(self, ss, es, data): | |
61 | # HACK! At the moment the number of probes is not handled correctly. | |
62 | # E.g. if an input file (-i foo.sr) has more than two probes enabled. | |
63 | # for (samplenum, (mosi, sck, x, y, z, a)) in data: | |
64 | # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: | |
65 | for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: | |
66 | ||
67 | # Sample data on rising SCK edges. | |
68 | if sck == self.oldsck: | |
69 | continue | |
70 | self.oldsck = sck | |
71 | if sck == 0: | |
72 | continue | |
73 | ||
74 | # If this is the first bit, save timestamp. | |
75 | if self.bitcount == 0: | |
76 | self.time = samplenum | |
77 | ||
78 | # Receive bit into our shift register. | |
79 | if mosi == 1: | |
80 | self.mosidata |= 1 << (7 - self.bitcount) | |
81 | ||
82 | self.bitcount += 1 | |
83 | ||
84 | # Continue to receive if not a byte yet. | |
85 | if self.bitcount != 8: | |
86 | continue | |
87 | ||
88 | # self.put(0, 0, self.out_proto, out_proto) # TODO | |
89 | self.put(0, 0, self.out_ann, [0, ['0x%02x' % self.mosidata]]) | |
90 | ||
91 | # Reset decoder state. | |
92 | self.mosidata = 0 | |
93 | self.bitcount = 0 | |
94 | ||
95 | # Keep stats for summary. | |
96 | self.bytesreceived += 1 | |
97 |