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ed5f826a | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
ed5f826a | 3 | ## |
6e256b1c | 4 | ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de> |
ed5f826a UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
ed5f826a UH |
21 | import sigrokdecode as srd |
22 | ||
ed5f826a UH |
23 | # Return the specified BCD number (max. 8 bits) as integer. |
24 | def bcd2int(b): | |
25 | return (b & 0x0f) + ((b >> 4) * 10) | |
26 | ||
27 | class Decoder(srd.Decoder): | |
28 | api_version = 1 | |
29 | id = 'rtc8564' | |
30 | name = 'RTC-8564' | |
31 | longname = 'Epson RTC-8564 JE/NB' | |
a465436e | 32 | desc = 'Realtime clock module protocol.' |
ed5f826a UH |
33 | license = 'gplv2+' |
34 | inputs = ['i2c'] | |
35 | outputs = ['rtc8564'] | |
36 | probes = [] | |
b77614bc | 37 | optional_probes = [ |
847e488b UH |
38 | {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'}, |
39 | {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'}, | |
40 | {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'}, | |
ed5f826a UH |
41 | ] |
42 | options = {} | |
43 | annotations = [ | |
a4289441 UH |
44 | ['reg-0x00', 'Register 0x00'], |
45 | ['reg-0x01', 'Register 0x01'], | |
46 | ['reg-0x02', 'Register 0x02'], | |
47 | ['reg-0x03', 'Register 0x03'], | |
48 | ['reg-0x04', 'Register 0x04'], | |
49 | ['reg-0x05', 'Register 0x05'], | |
50 | ['reg-0x06', 'Register 0x06'], | |
51 | ['reg-0x07', 'Register 0x07'], | |
52 | ['reg-0x08', 'Register 0x08'], | |
53 | ['read', 'Read date/time'], | |
54 | ['write', 'Write date/time'], | |
3161ab5a | 55 | ['bits', 'Bits'], |
ed5f826a | 56 | ] |
3161ab5a UH |
57 | annotation_rows = ( |
58 | ('bits', 'Bits', (11,)), | |
59 | ('regs', 'Registers', tuple(range(0, 8 + 1))), | |
60 | ('date-time', 'Date/time', (9, 10)), | |
61 | ) | |
ed5f826a UH |
62 | |
63 | def __init__(self, **kwargs): | |
2b716038 | 64 | self.state = 'IDLE' |
ed5f826a UH |
65 | self.hours = -1 |
66 | self.minutes = -1 | |
67 | self.seconds = -1 | |
68 | self.days = -1 | |
3d190141 | 69 | self.weekdays = -1 |
ed5f826a UH |
70 | self.months = -1 |
71 | self.years = -1 | |
72 | ||
8915b346 | 73 | def start(self): |
c515eed7 | 74 | # self.out_python = self.register(srd.OUTPUT_PYTHON) |
be465111 | 75 | self.out_ann = self.register(srd.OUTPUT_ANN) |
ed5f826a | 76 | |
ed5f826a UH |
77 | def putx(self, data): |
78 | self.put(self.ss, self.es, self.out_ann, data) | |
79 | ||
80 | def handle_reg_0x00(self, b): # Control register 1 | |
81 | pass | |
82 | ||
83 | def handle_reg_0x01(self, b): # Control register 2 | |
84 | ti_tp = 1 if (b & (1 << 4)) else 0 | |
85 | af = 1 if (b & (1 << 3)) else 0 | |
86 | tf = 1 if (b & (1 << 2)) else 0 | |
87 | aie = 1 if (b & (1 << 1)) else 0 | |
88 | tie = 1 if (b & (1 << 0)) else 0 | |
89 | ||
90 | ann = '' | |
91 | ||
92 | s = 'repeated' if ti_tp else 'single-shot' | |
93 | ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\ | |
94 | 'events\n' % (ti_tp, s) | |
95 | s = '' if af else 'no ' | |
96 | ann += 'AF = %d: %salarm interrupt detected\n' % (af, s) | |
97 | s = '' if tf else 'no ' | |
98 | ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s) | |
99 | s = 'enabled' if aie else 'prohibited' | |
100 | ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\ | |
101 | 'occurs\n' % (aie, s) | |
102 | s = 'enabled' if tie else 'prohibited' | |
103 | ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\ | |
104 | 'event occurs\n' % (tie, s) | |
105 | ||
a4289441 | 106 | self.putx([1, [ann]]) |
ed5f826a UH |
107 | |
108 | def handle_reg_0x02(self, b): # Seconds / Voltage-low flag | |
6e256b1c UH |
109 | s = self.seconds = bcd2int(b & 0x7f) |
110 | self.putx([2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s]]) | |
ed5f826a | 111 | vl = 1 if (b & (1 << 7)) else 0 |
6e256b1c UH |
112 | self.putx([11, ['Voltage low: %d' % vl, 'Volt low: %d' % vl, |
113 | 'VL: %d' % vl]]) | |
ed5f826a UH |
114 | |
115 | def handle_reg_0x03(self, b): # Minutes | |
6e256b1c UH |
116 | m = self.minutes = bcd2int(b & 0x7f) |
117 | self.putx([3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m]]) | |
ed5f826a UH |
118 | |
119 | def handle_reg_0x04(self, b): # Hours | |
6e256b1c UH |
120 | h = self.hours = bcd2int(b & 0x3f) |
121 | self.putx([4, ['Hour: %d' % h, 'H: %d' % h]]) | |
ed5f826a UH |
122 | |
123 | def handle_reg_0x05(self, b): # Days | |
6e256b1c UH |
124 | d = self.days = bcd2int(b & 0x3f) |
125 | self.putx([5, ['Day: %d' % d, 'D: %d' % d]]) | |
ed5f826a | 126 | |
3d190141 | 127 | def handle_reg_0x06(self, b): # Weekdays |
6e256b1c UH |
128 | w = self.weekdays = bcd2int(b & 0x07) |
129 | self.putx([6, ['Weekday: %d' % w, 'WD: %d' % w]]) | |
ed5f826a UH |
130 | |
131 | def handle_reg_0x07(self, b): # Months / century | |
132 | # TODO: Handle century bit. | |
6e256b1c UH |
133 | m = self.months = bcd2int(b & 0x1f) |
134 | self.putx([7, ['Month: %d' % m, 'Mon: %d' % m]]) | |
ed5f826a UH |
135 | |
136 | def handle_reg_0x08(self, b): # Years | |
6e256b1c UH |
137 | y = self.years = bcd2int(b & 0xff) |
138 | self.putx([8, ['Year: %d' % y, 'Y: %d' % y]]) | |
ed5f826a UH |
139 | |
140 | def handle_reg_0x09(self, b): # Alarm, minute | |
141 | pass | |
142 | ||
143 | def handle_reg_0x0a(self, b): # Alarm, hour | |
144 | pass | |
145 | ||
146 | def handle_reg_0x0b(self, b): # Alarm, day | |
147 | pass | |
148 | ||
149 | def handle_reg_0x0c(self, b): # Alarm, weekday | |
150 | pass | |
151 | ||
152 | def handle_reg_0x0d(self, b): # CLKOUT output | |
153 | pass | |
154 | ||
155 | def handle_reg_0x0e(self, b): # Timer setting | |
156 | pass | |
157 | ||
158 | def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer | |
159 | pass | |
160 | ||
161 | def decode(self, ss, es, data): | |
1b75abfd | 162 | cmd, databyte = data |
ed5f826a | 163 | |
00197484 | 164 | # Store the start/end samples of this I²C packet. |
ed5f826a UH |
165 | self.ss, self.es = ss, es |
166 | ||
167 | # State machine. | |
2b716038 | 168 | if self.state == 'IDLE': |
00197484 | 169 | # Wait for an I²C START condition. |
ed5f826a UH |
170 | if cmd != 'START': |
171 | return | |
2b716038 | 172 | self.state = 'GET SLAVE ADDR' |
ed5f826a | 173 | self.block_start_sample = ss |
2b716038 | 174 | elif self.state == 'GET SLAVE ADDR': |
ed5f826a UH |
175 | # Wait for an address write operation. |
176 | # TODO: We should only handle packets to the RTC slave (0xa2/0xa3). | |
177 | if cmd != 'ADDRESS WRITE': | |
178 | return | |
2b716038 UH |
179 | self.state = 'GET REG ADDR' |
180 | elif self.state == 'GET REG ADDR': | |
ed5f826a UH |
181 | # Wait for a data write (master selects the slave register). |
182 | if cmd != 'DATA WRITE': | |
183 | return | |
184 | self.reg = databyte | |
2b716038 UH |
185 | self.state = 'WRITE RTC REGS' |
186 | elif self.state == 'WRITE RTC REGS': | |
ed5f826a UH |
187 | # If we see a Repeated Start here, it's probably an RTC read. |
188 | if cmd == 'START REPEAT': | |
2b716038 | 189 | self.state = 'READ RTC REGS' |
ed5f826a UH |
190 | return |
191 | # Otherwise: Get data bytes until a STOP condition occurs. | |
192 | if cmd == 'DATA WRITE': | |
193 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
194 | handle_reg(databyte) | |
195 | self.reg += 1 | |
196 | # TODO: Check for NACK! | |
197 | elif cmd == 'STOP': | |
198 | # TODO: Handle read/write of only parts of these items. | |
199 | d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, | |
200 | self.years, self.hours, self.minutes, self.seconds) | |
201 | self.put(self.block_start_sample, es, self.out_ann, | |
6e256b1c UH |
202 | [9, ['Write date/time: %s' % d, 'Write: %s' % d, |
203 | 'W: %s' % d]]) | |
2b716038 | 204 | self.state = 'IDLE' |
ed5f826a UH |
205 | else: |
206 | pass # TODO | |
2b716038 | 207 | elif self.state == 'READ RTC REGS': |
ed5f826a UH |
208 | # Wait for an address read operation. |
209 | # TODO: We should only handle packets to the RTC slave (0xa2/0xa3). | |
210 | if cmd == 'ADDRESS READ': | |
2b716038 | 211 | self.state = 'READ RTC REGS2' |
ed5f826a UH |
212 | return |
213 | else: | |
e4f82268 | 214 | pass # TODO |
2b716038 | 215 | elif self.state == 'READ RTC REGS2': |
ed5f826a UH |
216 | if cmd == 'DATA READ': |
217 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
218 | handle_reg(databyte) | |
219 | self.reg += 1 | |
220 | # TODO: Check for NACK! | |
221 | elif cmd == 'STOP': | |
222 | d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, | |
223 | self.years, self.hours, self.minutes, self.seconds) | |
224 | self.put(self.block_start_sample, es, self.out_ann, | |
6e256b1c UH |
225 | [10, ['Read date/time: %s' % d, 'Read: %s' % d, |
226 | 'R: %s' % d]]) | |
2b716038 | 227 | self.state = 'IDLE' |
ed5f826a UH |
228 | else: |
229 | pass # TODO? | |
230 | else: | |
0eeeb544 | 231 | raise Exception('Invalid state: %s' % self.state) |
ed5f826a | 232 |