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mx25lxx05d: Define annotation rows.
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1b1c914f 1##
50bd5d25 2## This file is part of the libsigrokdecode project.
1b1c914f 3##
9389f2c1 4## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
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5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
677d597b 21import sigrokdecode as srd
1b1c914f 22
4772a846 23# Dict which maps command IDs to their names and descriptions.
1b1c914f 24cmds = {
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25 0x06: ('WREN', 'Write enable'),
26 0x04: ('WRDI', 'Write disable'),
27 0x9f: ('RDID', 'Read identification'),
28 0x05: ('RDSR', 'Read status register'),
29 0x01: ('WRSR', 'Write status register'),
30 0x03: ('READ', 'Read data'),
781ef945 31 0x0b: ('FAST/READ', 'Fast read data'),
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32 0xbb: ('2READ', '2x I/O read'),
33 0x20: ('SE', 'Sector erase'),
34 0xd8: ('BE', 'Block erase'),
35 0x60: ('CE', 'Chip erase'),
36 0xc7: ('CE2', 'Chip erase'), # Alternative command ID
37 0x02: ('PP', 'Page program'),
38 0xad: ('CP', 'Continuously program mode'),
39 0xb9: ('DP', 'Deep power down'),
781ef945 40 0xab: ('RDP/RES', 'Release from deep powerdown / Read electronic ID'),
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41 0x90: ('REMS', 'Read electronic manufacturer & device ID'),
42 0xef: ('REMS2', 'Read ID for 2x I/O mode'),
43 0xb1: ('ENSO', 'Enter secured OTP'),
44 0xc1: ('EXSO', 'Exit secured OTP'),
45 0x2b: ('RDSCUR', 'Read security register'),
46 0x2f: ('WRSCUR', 'Write security register'),
47 0x70: ('ESRY', 'Enable SO to output RY/BY#'),
48 0x80: ('DSRY', 'Disable SO to output RY/BY#'),
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49}
50
51device_name = {
52 0x14: 'MX25L1605D',
53 0x15: 'MX25L3205D',
54 0x16: 'MX25L6405D',
55}
56
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57def cmd_annotation_classes():
58 return [[cmd[0].lower(), cmd[1]] for cmd in cmds.values()]
59
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60def decode_status_reg(data):
61 # TODO: Additional per-bit(s) self.put() calls with correct start/end.
62
63 # Bits[0:0]: WIP (write in progress)
64 s = 'W' if (data & (1 << 0)) else 'No w'
65 ret = '%srite operation in progress.\n' % s
66
67 # Bits[1:1]: WEL (write enable latch)
68 s = '' if (data & (1 << 1)) else 'not '
69 ret += 'Internal write enable latch is %sset.\n' % s
70
71 # Bits[5:2]: Block protect bits
72 # TODO: More detailed decoding (chip-dependent).
73 ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
74
75 # Bits[6:6]: Continuously program mode (CP mode)
76 s = '' if (data & (1 << 6)) else 'not '
77 ret += 'Device is %sin continuously program mode (CP mode).\n' % s
78
79 # Bits[7:7]: SRWD (status register write disable)
cd287c56 80 s = 'not ' if (data & (1 << 7)) else ''
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81 ret += 'Status register writes are %sallowed.\n' % s
82
83 return ret
84
677d597b 85class Decoder(srd.Decoder):
a2c2afd9 86 api_version = 1
1b1c914f 87 id = 'mx25lxx05d'
9a12a6e7 88 name = 'MX25Lxx05D'
3d3da57d 89 longname = 'Macronix MX25Lxx05D'
a465436e 90 desc = 'SPI (NOR) flash chip protocol.'
1b1c914f 91 license = 'gplv2+'
385508e9 92 inputs = ['spi', 'logic']
1b1c914f 93 outputs = ['mx25lxx05d']
385508e9 94 probes = []
b77614bc 95 optional_probes = [
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96 {'id': 'hold', 'name': 'HOLD#', 'desc': 'Pause device w/o deselecting it'},
97 {'id': 'wp_acc', 'name': 'WP#/ACC', 'desc': 'Write protect'},
385508e9 98 ]
781ef945 99 options = {}
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100 annotations = cmd_annotation_classes() + [
101 ['bits', 'Bits'],
102 ['bits2', 'Bits2'],
103 ['warnings', 'Warnings'],
9b4d8a57 104 ]
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105 annotation_rows = (
106 ('bits', 'Bits', (24, 25)),
107 ('commands', 'Commands', tuple(range(23 + 1))),
108 ('warnings', 'Warnings', (26,)),
109 )
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110
111 def __init__(self, **kwargs):
4772a846 112 self.state = None
781ef945 113 self.cmdstate = 1
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114 self.addr = 0
115 self.data = []
1b1c914f 116
8915b346 117 def start(self):
c515eed7 118 # self.out_python = self.register(srd.OUTPUT_PYTHON)
be465111 119 self.out_ann = self.register(srd.OUTPUT_ANN)
1b1c914f 120
385508e9 121 def putx(self, data):
ee3e279c 122 # Simplification, most annotations span exactly one SPI byte/packet.
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123 self.put(self.ss, self.es, self.out_ann, data)
124
125 def handle_wren(self, mosi, miso):
781ef945 126 self.putx([0, ['Command: %s' % cmds[self.state][1]]])
4772a846 127 self.state = None
1b1c914f 128
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129 def handle_wrdi(self, mosi, miso):
130 pass # TODO
131
1b1c914f 132 # TODO: Check/display device ID / name
9b4d8a57 133 def handle_rdid(self, mosi, miso):
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134 if self.cmdstate == 1:
135 # Byte 1: Master sends command ID.
9b4d8a57 136 self.start_sample = self.ss
9389f2c1 137 self.putx([2, ['Command: %s' % cmds[self.state][1]]])
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138 elif self.cmdstate == 2:
139 # Byte 2: Slave sends the JEDEC manufacturer ID.
9389f2c1 140 self.putx([2, ['Manufacturer ID: 0x%02x' % miso]])
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141 elif self.cmdstate == 3:
142 # Byte 3: Slave sends the memory type (0x20 for this chip).
9389f2c1 143 self.putx([2, ['Memory type: 0x%02x' % miso]])
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144 elif self.cmdstate == 4:
145 # Byte 4: Slave sends the device ID.
9b4d8a57 146 self.device_id = miso
9389f2c1 147 self.putx([2, ['Device ID: 0x%02x' % miso]])
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148
149 if self.cmdstate == 4:
150 # TODO: Check self.device_id is valid & exists in device_names.
151 # TODO: Same device ID? Check!
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152 d = 'Device: Macronix %s' % device_name[self.device_id]
153 self.put(self.start_sample, self.es, self.out_ann, [0, [d]])
4772a846 154 self.state = None
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155 else:
156 self.cmdstate += 1
157
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158 def handle_rdsr(self, mosi, miso):
159 # Read status register: Master asserts CS#, sends RDSR command,
160 # reads status register byte. If CS# is kept asserted, the status
161 # register can be read continuously / multiple times in a row.
162 # When done, the master de-asserts CS# again.
163 if self.cmdstate == 1:
164 # Byte 1: Master sends command ID.
9389f2c1 165 self.putx([3, ['Command: %s' % cmds[self.state][1]]])
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166 elif self.cmdstate >= 2:
167 # Bytes 2-x: Slave sends status register as long as master clocks.
168 if self.cmdstate <= 3: # TODO: While CS# asserted.
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169 self.putx([24, ['Status register: 0x%02x' % miso]])
170 self.putx([25, [decode_status_reg(miso)]])
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171
172 if self.cmdstate == 3: # TODO: If CS# got de-asserted.
173 self.state = None
174 return
175
176 self.cmdstate += 1
177
178 def handle_wrsr(self, mosi, miso):
179 pass # TODO
180
181 def handle_read(self, mosi, miso):
182 # Read data bytes: Master asserts CS#, sends READ command, sends
183 # 3-byte address, reads >= 1 data bytes, de-asserts CS#.
184 if self.cmdstate == 1:
185 # Byte 1: Master sends command ID.
9389f2c1 186 self.putx([5, ['Command: %s' % cmds[self.state][1]]])
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187 elif self.cmdstate in (2, 3, 4):
188 # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
189 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
190 # self.putx([0, ['Read address, byte %d: 0x%02x' % \
191 # (4 - self.cmdstate, mosi)]])
192 if self.cmdstate == 4:
9389f2c1 193 self.putx([24, ['Read address: 0x%06x' % self.addr]])
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194 self.addr = 0
195 elif self.cmdstate >= 5:
196 # Bytes 5-x: Master reads data bytes (until CS# de-asserted).
197 # TODO: For now we hardcode 256 bytes per READ command.
198 if self.cmdstate <= 256 + 4: # TODO: While CS# asserted.
199 self.data.append(miso)
200 # self.putx([0, ['New read byte: 0x%02x' % miso]])
201
202 if self.cmdstate == 256 + 4: # TODO: If CS# got de-asserted.
203 # s = ', '.join(map(hex, self.data))
204 s = ''.join(map(chr, self.data))
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205 self.putx([24, ['Read data']])
206 self.putx([25, ['Read data: %s' % s]])
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207 self.data = []
208 self.state = None
209 return
210
211 self.cmdstate += 1
212
213 def handle_fast_read(self, mosi, miso):
214 pass # TODO
215
216 def handle_2read(self, mosi, miso):
217 pass # TODO
218
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219 # TODO: Warn/abort if we don't see the necessary amount of bytes.
220 # TODO: Warn if WREN was not seen before.
9b4d8a57 221 def handle_se(self, mosi, miso):
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222 if self.cmdstate == 1:
223 # Byte 1: Master sends command ID.
224 self.addr = 0
9b4d8a57 225 self.start_sample = self.ss
9389f2c1 226 self.putx([8, ['Command: %s' % cmds[self.state][1]]])
1b1c914f 227 elif self.cmdstate in (2, 3, 4):
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228 # Bytes 2/3/4: Master sends sectror address (24bits, MSB-first).
229 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
230 # self.putx([0, ['Sector address, byte %d: 0x%02x' % \
231 # (4 - self.cmdstate, mosi)]])
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232
233 if self.cmdstate == 4:
87e574b7 234 d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
9389f2c1 235 self.put(self.start_sample, self.es, self.out_ann, [24, [d]])
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236 # TODO: Max. size depends on chip, check that too if possible.
237 if self.addr % 4096 != 0:
238 # Sector addresses must be 4K-aligned (same for all 3 chips).
173c919c 239 d = 'Warning: Invalid sector address!'
9389f2c1 240 self.put(self.start_sample, self.es, self.out_ann, [101, [d]])
4772a846 241 self.state = None
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242 else:
243 self.cmdstate += 1
244
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245 def handle_be(self, mosi, miso):
246 pass # TODO
247
248 def handle_ce(self, mosi, miso):
249 pass # TODO
250
251 def handle_ce2(self, mosi, miso):
252 pass # TODO
253
254 def handle_pp(self, mosi, miso):
255 # Page program: Master asserts CS#, sends PP command, sends 3-byte
256 # page address, sends >= 1 data bytes, de-asserts CS#.
257 if self.cmdstate == 1:
258 # Byte 1: Master sends command ID.
9389f2c1 259 self.putx([12, ['Command: %s' % cmds[self.state][1]]])
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260 elif self.cmdstate in (2, 3, 4):
261 # Bytes 2/3/4: Master sends page address (24bits, MSB-first).
262 self.addr |= (mosi << ((4 - self.cmdstate) * 8))
263 # self.putx([0, ['Page address, byte %d: 0x%02x' % \
264 # (4 - self.cmdstate, mosi)]])
265 if self.cmdstate == 4:
9389f2c1 266 self.putx([24, ['Page address: 0x%06x' % self.addr]])
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267 self.addr = 0
268 elif self.cmdstate >= 5:
269 # Bytes 5-x: Master sends data bytes (until CS# de-asserted).
270 # TODO: For now we hardcode 256 bytes per page / PP command.
271 if self.cmdstate <= 256 + 4: # TODO: While CS# asserted.
272 self.data.append(mosi)
273 # self.putx([0, ['New data byte: 0x%02x' % mosi]])
274
275 if self.cmdstate == 256 + 4: # TODO: If CS# got de-asserted.
276 # s = ', '.join(map(hex, self.data))
277 s = ''.join(map(chr, self.data))
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278 self.putx([24, ['Page data']])
279 self.putx([25, ['Page data: %s' % s]])
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280 self.data = []
281 self.state = None
282 return
283
284 self.cmdstate += 1
285
286 def handle_cp(self, mosi, miso):
287 pass # TODO
288
289 def handle_dp(self, mosi, miso):
290 pass # TODO
291
292 def handle_rdp_res(self, mosi, miso):
293 pass # TODO
294
9b4d8a57 295 def handle_rems(self, mosi, miso):
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296 if self.cmdstate == 1:
297 # Byte 1: Master sends command ID.
9b4d8a57 298 self.start_sample = self.ss
9389f2c1 299 self.putx([16, ['Command: %s' % cmds[self.state][1]]])
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300 elif self.cmdstate in (2, 3):
301 # Bytes 2/3: Master sends two dummy bytes.
302 # TODO: Check dummy bytes? Check reply from device?
9389f2c1 303 self.putx([24, ['Dummy byte: %s' % mosi]])
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304 elif self.cmdstate == 4:
305 # Byte 4: Master sends 0x00 or 0x01.
306 # 0x00: Master wants manufacturer ID as first reply byte.
307 # 0x01: Master wants device ID as first reply byte.
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308 self.manufacturer_id_first = True if (mosi == 0x00) else False
309 d = 'manufacturer' if (mosi == 0x00) else 'device'
9389f2c1 310 self.putx([24, ['Master wants %s ID first' % d]])
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311 elif self.cmdstate == 5:
312 # Byte 5: Slave sends manufacturer ID (or device ID).
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313 self.ids = [miso]
314 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
9389f2c1 315 self.putx([24, ['%s ID' % d]])
9b4d8a57 316 elif self.cmdstate == 6:
1b1c914f 317 # Byte 6: Slave sends device ID (or manufacturer ID).
7f7ea759 318 self.ids.append(miso)
9b4d8a57 319 d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
9389f2c1 320 self.putx([24, ['%s ID' % d]])
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321
322 if self.cmdstate == 6:
9b4d8a57 323 self.end_sample = self.es
1b1c914f 324 id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
9389f2c1 325 self.putx([24, ['Device: Macronix %s' % device_name[id]]])
4772a846 326 self.state = None
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327 else:
328 self.cmdstate += 1
329
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330 def handle_rems2(self, mosi, miso):
331 pass # TODO
e4022299 332
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333 def handle_enso(self, mosi, miso):
334 pass # TODO
e4022299 335
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336 def handle_exso(self, mosi, miso):
337 pass # TODO
e4022299 338
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339 def handle_rdscur(self, mosi, miso):
340 pass # TODO
e4022299 341
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342 def handle_wrscur(self, mosi, miso):
343 pass # TODO
e4022299 344
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345 def handle_esry(self, mosi, miso):
346 pass # TODO
1b1c914f 347
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348 def handle_dsry(self, mosi, miso):
349 pass # TODO
5ebb76fe 350
2b9837d9 351 def decode(self, ss, es, data):
1b1c914f 352
9b4d8a57 353 ptype, mosi, miso = data
1b1c914f 354
e4022299 355 # if ptype == 'DATA':
781ef945 356 # self.putx([0, ['MOSI: 0x%02x, MISO: 0x%02x' % (mosi, miso)]])
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357
358 # if ptype == 'CS-CHANGE':
359 # if mosi == 1 and miso == 0:
781ef945 360 # self.putx([0, ['Asserting CS#']])
e4022299 361 # elif mosi == 0 and miso == 1:
781ef945 362 # self.putx([0, ['De-asserting CS#']])
e4022299 363
3e3c0330 364 if ptype != 'DATA':
9b4d8a57 365 return
1b1c914f 366
e4022299 367 self.ss, self.es = ss, es
1b1c914f 368
9b4d8a57 369 # If we encountered a known chip command, enter the resp. state.
4772a846 370 if self.state == None:
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371 self.state = mosi
372 self.cmdstate = 1
1b1c914f 373
9b4d8a57 374 # Handle commands.
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375 if self.state in cmds:
376 s = 'handle_%s' % cmds[self.state][0].lower().replace('/', '_')
377 handle_reg = getattr(self, s)
4772a846 378 handle_reg(mosi, miso)
9b4d8a57 379 else:
9389f2c1 380 self.putx([24, ['Unknown command: 0x%02x' % mosi]])
4772a846 381 self.state = None
1b1c914f 382