[libsigrokdecode.git] / decoders / lfast / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2020 Soeren Apel <soeren@apelpie.net>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd
from common.srdhelper import bitpack
import decimal

'''
OUTPUT_PYTHON format:

[<data>] where <data> is the payload contained between the LFAST header and
the LFAST stop bit. It's an array of bytes. 
'''

ann_bit, ann_sync, ann_header, ann_payload, ann_stopbit, ann_warning = range(6)
state_sync, state_header, state_payload, state_stopbit = range(4)

class Decoder(srd.Decoder):
    api_version = 3
    id = 'lfast'
    name = 'LFAST'
    longname = 'NXP LFAST interface'
    desc = 'Differential high-speed P2P interface'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['lfast']
    tags = ['Embedded/industrial']
    channels = (
        {'id': 'data', 'name': 'Data', 'desc': 'TXP or RXP'},
    )
    annotations = (
        ('bit', 'Bits'),
        ('sync', 'Sync Pattern'),
        ('header', 'Header'),
        ('payload', 'Payload'),
        ('stop', 'Stop Bit'),
        ('warning', 'Warning'),
    )
    annotation_rows = (
        ('bits', 'Bits', (ann_bit,)),
        ('fields', 'Fields', (ann_sync, ann_header, ann_payload, ann_stopbit,)),
        ('warnings', 'Warnings', (ann_warning,)),
    )

    def __init__(self):
        decimal.getcontext().rounding = decimal.ROUND_HALF_UP
        self.reset()

    def reset(self):
        self.ss = self.es = 0
        self.ss_payload = self.es_payload = 0
        self.bits = []
        self.payload = []
        self.bit_len = 0
        self.timeout = 0
        self.state = state_sync

    def metadata(self, key, value):
        pass

    def start(self):
        self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def put_ann(self, ss, es, ann_class, value):
        self.put(ss, es, self.out_ann, [ann_class, value])

    def put_payload(self):
        self.put(self.ss_payload, self.es_payload, self.out_python, self.payload)

    def handle_sync(self):
        if len(self.bits) == 1:
            self.ss_sync = self.ss_bit

        if len(self.bits) == 16:
            value = bitpack(self.bits)
            if value == 0xA84B:
                self.put_ann(self.ss_sync, self.es_bit, ann_sync, ['Sync OK'])
            else:
                self.put_ann(self.ss_sync, self.es_bit, ann_warning, ['Wrong Sync Value: {:2X}'.format(value)])

            self.bits = []
            self.state = state_header

    def handle_header(self):
        if len(self.bits) == 1:
            self.ss_header = self.ss_bit

        if len(self.bits) == 8:
            value = bitpack(self.bits)
            self.put_ann(self.ss_header, self.es_bit, ann_header, ['{:2X}'.format(value)])
            self.bits = []
            self.state = state_payload

    def handle_payload(self):
        # 8 bit times without state change are possible (8 low bits) but when
        # there are 9 bit times without state change, we should have seen the
        # stop bit - and only the stop bit
        self.timeout = int(9 * self.bit_len)

        if len(self.bits) == 1:
            self.ss_byte = self.ss_bit
            if self.ss_payload == 0:
                self.ss_payload = self.ss_bit

        if len(self.bits) == 8:
            value = bitpack(self.bits)
            self.put_ann(self.ss_byte, self.es_bit, ann_payload, ['{:2X}'.format(value)])
            self.bits = []
            self.payload.append(value)
            self.es_payload = self.es_bit

    def handle_stopbit(self):
        if len(self.bits) > 1:
            self.put_ann(self.ss_bit, self.es_bit, ann_warning, ['Expected only the stop bit, got {} bits'.format(len(self.bits))])
        else:
            if self.bits[0] == 1: 
                self.put_ann(self.ss_bit, self.es_bit, ann_stopbit, ['Stop Bit', 'Stop', 'S'])
            else:
                self.put_ann(self.ss_bit, self.es_bit, ann_warning, ['Stop Bit must be 1', 'Stop not 1', 'S'])

        # We send the payload out regardless of the stop bit's status so that
        # any intermediate results can be decoded by a stacked decoder
        self.put_payload()
        self.payload = []
        self.ss_payload = 0
        
        self.timeout = 0
        self.bits = []
        self.state = state_sync

    def decode(self):
        while True:
            if self.timeout == 0:
                rising_edge, = self.wait({0: 'e'})
            else:
                rising_edge, = self.wait([{0: 'e'}, {'skip': self.timeout}])

            # If this is the first bit, we only update ss
            if self.ss == 0:
                self.ss = self.samplenum
                continue
        
            self.es = self.samplenum

            # Check for the stop bit if this is a timeout condition
            if (self.timeout > 0) and (self.es - self.ss >= self.timeout):
                self.handle_stopbit()
                continue

            # We use the first bit to deduce the bit length
            if self.bit_len == 0:
                self.bit_len = self.es - self.ss

            # Determine number of bits covered by this edge
            bit_count = (self.es - self.ss) / self.bit_len
            bit_count = int(decimal.Decimal(bit_count).to_integral_value())

            bit_value = '0' if rising_edge else '1'

            divided_len = (self.es - self.ss) / bit_count
            for i in range(bit_count):
                self.ss_bit = int(self.ss + i * divided_len)
                self.es_bit = int(self.ss_bit + divided_len)
                self.put_ann(self.ss_bit, self.es_bit, ann_bit, [bit_value])

                # Place the new bit at the front of the bit list
                self.bits.insert(0, (0 if rising_edge else 1))

                if self.state == state_sync:
                    self.handle_sync()
                elif self.state == state_header:
                    self.handle_header()
                elif self.state == state_payload:
                    self.handle_payload()

            self.ss = self.samplenum
Commit	Line	Data
c5a2f0b4 SA	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2020 Soeren Apel <soeren@apelpie.net>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	##
	19
	20	import sigrokdecode as srd
	21	from common.srdhelper import bitpack
	22	import decimal
	23
	24	'''
	25	OUTPUT_PYTHON format:
	26
	27	[<data>] where <data> is the payload contained between the LFAST header and
	28	the LFAST stop bit. It's an array of bytes.
	29	'''
	30
	31	ann_bit, ann_sync, ann_header, ann_payload, ann_stopbit, ann_warning = range(6)
	32	state_sync, state_header, state_payload, state_stopbit = range(4)
	33
	34	class Decoder(srd.Decoder):
	35	api_version = 3
	36	id = 'lfast'
	37	name = 'LFAST'
	38	longname = 'NXP LFAST interface'
	39	desc = 'Differential high-speed P2P interface'
	40	license = 'gplv2+'
	41	inputs = ['logic']
	42	outputs = ['lfast']
	43	tags = ['Embedded/industrial']
	44	channels = (
	45	{'id': 'data', 'name': 'Data', 'desc': 'TXP or RXP'},
	46	)
	47	annotations = (
	48	('bit', 'Bits'),
	49	('sync', 'Sync Pattern'),
	50	('header', 'Header'),
	51	('payload', 'Payload'),
	52	('stop', 'Stop Bit'),
	53	('warning', 'Warning'),
	54	)
	55	annotation_rows = (
	56	('bits', 'Bits', (ann_bit,)),
	57	('fields', 'Fields', (ann_sync, ann_header, ann_payload, ann_stopbit,)),
	58	('warnings', 'Warnings', (ann_warning,)),
	59	)
	60
	61	def __init__(self):
	62	decimal.getcontext().rounding = decimal.ROUND_HALF_UP
	63	self.reset()
	64
65	def reset(self):
66	self.ss = self.es = 0
67	self.ss_payload = self.es_payload = 0
68	self.bits = []
69	self.payload = []
70	self.bit_len = 0
71	self.timeout = 0
72	self.state = state_sync
73
74	def metadata(self, key, value):
75	pass
76
77	def start(self):
78	self.out_python = self.register(srd.OUTPUT_PYTHON)
79	self.out_ann = self.register(srd.OUTPUT_ANN)
80
81	def put_ann(self, ss, es, ann_class, value):
82	self.put(ss, es, self.out_ann, [ann_class, value])
83
84	def put_payload(self):
85	self.put(self.ss_payload, self.es_payload, self.out_python, self.payload)
86
87	def handle_sync(self):
88	if len(self.bits) == 1:
89	self.ss_sync = self.ss_bit
90
91	if len(self.bits) == 16:
92	value = bitpack(self.bits)
93	if value == 0xA84B:
94	self.put_ann(self.ss_sync, self.es_bit, ann_sync, ['Sync OK'])
95	else:
96	self.put_ann(self.ss_sync, self.es_bit, ann_warning, ['Wrong Sync Value: {:2X}'.format(value)])
97
98	self.bits = []
99	self.state = state_header
100
101	def handle_header(self):
102	if len(self.bits) == 1:
103	self.ss_header = self.ss_bit
104
105	if len(self.bits) == 8:
106	value = bitpack(self.bits)
107	self.put_ann(self.ss_header, self.es_bit, ann_header, ['{:2X}'.format(value)])
108	self.bits = []
109	self.state = state_payload
110
111	def handle_payload(self):
112	# 8 bit times without state change are possible (8 low bits) but when
113	# there are 9 bit times without state change, we should have seen the
114	# stop bit - and only the stop bit
115	self.timeout = int(9 * self.bit_len)
116
117	if len(self.bits) == 1:
118	self.ss_byte = self.ss_bit
119	if self.ss_payload == 0:
120	self.ss_payload = self.ss_bit
121
122	if len(self.bits) == 8:
123	value = bitpack(self.bits)
124	self.put_ann(self.ss_byte, self.es_bit, ann_payload, ['{:2X}'.format(value)])
125	self.bits = []
126	self.payload.append(value)
127	self.es_payload = self.es_bit
128
129	def handle_stopbit(self):
130	if len(self.bits) > 1:
131	self.put_ann(self.ss_bit, self.es_bit, ann_warning, ['Expected only the stop bit, got {} bits'.format(len(self.bits))])
132	else:
133	if self.bits[0] == 1:
134	self.put_ann(self.ss_bit, self.es_bit, ann_stopbit, ['Stop Bit', 'Stop', 'S'])
135	else:
136	self.put_ann(self.ss_bit, self.es_bit, ann_warning, ['Stop Bit must be 1', 'Stop not 1', 'S'])
137
138	# We send the payload out regardless of the stop bit's status so that
139	# any intermediate results can be decoded by a stacked decoder
140	self.put_payload()
141	self.payload = []
142	self.ss_payload = 0
143
144	self.timeout = 0
145	self.bits = []
146	self.state = state_sync
147
148	def decode(self):
149	while True:
150	if self.timeout == 0:
151	rising_edge, = self.wait({0: 'e'})
152	else:
153	rising_edge, = self.wait([{0: 'e'}, {'skip': self.timeout}])
154
155	# If this is the first bit, we only update ss
156	if self.ss == 0:
157	self.ss = self.samplenum
158	continue
159
160	self.es = self.samplenum
161
162	# Check for the stop bit if this is a timeout condition
163	if (self.timeout > 0) and (self.es - self.ss >= self.timeout):
164	self.handle_stopbit()
165	continue
166
167	# We use the first bit to deduce the bit length
168	if self.bit_len == 0:
169	self.bit_len = self.es - self.ss
170
171	# Determine number of bits covered by this edge
172	bit_count = (self.es - self.ss) / self.bit_len
173	bit_count = int(decimal.Decimal(bit_count).to_integral_value())
174
175	bit_value = '0' if rising_edge else '1'
176
177	divided_len = (self.es - self.ss) / bit_count
178	for i in range(bit_count):
179	self.ss_bit = int(self.ss + i * divided_len)
180	self.es_bit = int(self.ss_bit + divided_len)
181	self.put_ann(self.ss_bit, self.es_bit, ann_bit, [bit_value])
182
183	# Place the new bit at the front of the bit list
184	self.bits.insert(0, (0 if rising_edge else 1))
185
186	if self.state == state_sync:
187	self.handle_sync()
188	elif self.state == state_header:
189	self.handle_header()
190	elif self.state == state_payload:
191	self.handle_payload()
192
193	self.ss = self.samplenum