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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2017 Marcus Comstedt <marcus@mc.pp.se>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, see <http://www.gnu.org/licenses/>.
18##
19
20import sigrokdecode as srd
21
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22step_wait_conds = (
23 [{2: 'f'}, {0: 'l', 1: 'h'}],
24 [{2: 'f'}, {0: 'h', 1: 'h'}, {1: 'l'}],
25 [{2: 'f'}, {0: 'f'}, {1: 'l'}],
26 [{2: 'f'}, {1: 'e'}],
27)
28
a92df5ba 29class Decoder(srd.Decoder):
483f2aff 30 api_version = 3
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31 id = 'iec'
32 name = 'IEC'
33 longname = 'Commodore bus'
34 desc = 'Commodore serial IEEE-488 (IEC) bus protocol.'
35 license = 'gplv2+'
36 inputs = ['logic']
37 outputs = ['gpib']
38 channels = (
39 {'id': 'data', 'name': 'DATA', 'desc': 'Data I/O'},
40 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
41 {'id': 'atn', 'name': 'ATN', 'desc': 'Attention'},
42 )
43 optional_channels = (
44 {'id': 'srq', 'name': 'SRQ', 'desc': 'Service request'},
45 )
46 annotations = (
47 ('items', 'Items'),
48 ('gpib', 'DAT/CMD'),
49 ('eoi', 'EOI'),
50 )
51 annotation_rows = (
52 ('bytes', 'Bytes', (0,)),
53 ('gpib', 'DAT/CMD', (1,)),
54 ('eoi', 'EOI', (2,)),
55 )
56
57 def __init__(self):
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58 self.reset()
59
60 def reset(self):
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61 self.saved_ATN = False
62 self.saved_EOI = False
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63 self.ss_item = self.es_item = None
64 self.step = 0
65 self.bits = 0
66 self.numbits = 0
67
68 def start(self):
69 self.out_ann = self.register(srd.OUTPUT_ANN)
70
71 def putb(self, data):
72 self.put(self.ss_item, self.es_item, self.out_ann, data)
73
74 def handle_bits(self):
75 # Output the saved item.
76 dbyte = self.bits
77 dATN = self.saved_ATN
78 dEOI = self.saved_EOI
79 self.es_item = self.samplenum
80 self.putb([0, ['%02X' % dbyte]])
81
82 # Encode item byte to GPIB convention.
83 self.strgpib = ' '
84 if dATN: # ATN, decode commands.
85 # Note: Commands < 0x20 are not used on IEC bus.
86 if dbyte == 0x01: self.strgpib = 'GTL'
87 if dbyte == 0x04: self.strgpib = 'SDC'
88 if dbyte == 0x05: self.strgpib = 'PPC'
89 if dbyte == 0x08: self.strgpib = 'GET'
90 if dbyte == 0x09: self.strgpib = 'TCT'
91 if dbyte == 0x11: self.strgpib = 'LLO'
92 if dbyte == 0x14: self.strgpib = 'DCL'
93 if dbyte == 0x15: self.strgpib = 'PPU'
94 if dbyte == 0x18: self.strgpib = 'SPE'
95 if dbyte == 0x19: self.strgpib = 'SPD'
96
97 if dbyte == 0x3f: self.strgpib = 'UNL'
98 if dbyte == 0x5f: self.strgpib = 'UNT'
99 if dbyte > 0x1f and dbyte < 0x3f: # Address listener.
100 self.strgpib = 'L' + chr(dbyte + 0x10)
101 if dbyte > 0x3f and dbyte < 0x5f: # Address talker.
102 self.strgpib = 'T' + chr(dbyte - 0x10)
103 if dbyte > 0x5f and dbyte < 0x70: # Channel reopen.
104 self.strgpib = 'R' + chr(dbyte - 0x30)
105 if dbyte > 0xdf and dbyte < 0xf0: # Channel close.
106 self.strgpib = 'C' + chr(dbyte - 0xb0)
107 if dbyte > 0xef: # Channel open.
108 self.strgpib = 'O' + chr(dbyte - 0xc0)
109 else:
110 if dbyte > 0x1f and dbyte < 0x7f:
111 self.strgpib = chr(dbyte)
112 if dbyte == 0x0a:
113 self.strgpib = 'LF'
114 if dbyte == 0x0d:
115 self.strgpib = 'CR'
116
117 self.putb([1, [self.strgpib]])
118 self.strEOI = ' '
119 if dEOI:
120 self.strEOI = 'EOI'
121 self.putb([2, [self.strEOI]])
122
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123 def decode(self):
124 while True:
a92df5ba 125
483f2aff 126 data, clk, atn, srq = self.wait(step_wait_conds[self.step])
a92df5ba 127
483f2aff 128 if self.matched[0]:
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129 # Falling edge on ATN, reset step.
130 self.step = 0
131
132 if self.step == 0:
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133 # Don't use self.matched[1] here since we might come from
134 # a step with different conds due to the code above.
135 if data == 0 and clk == 1:
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136 # Rising edge on CLK while DATA is low: Ready to send.
137 self.step = 1
138 elif self.step == 1:
483f2aff 139 if data == 1 and clk == 1:
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140 # Rising edge on DATA while CLK is high: Ready for data.
141 self.ss_item = self.samplenum
483f2aff 142 self.saved_ATN = not atn
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143 self.saved_EOI = False
144 self.bits = 0
145 self.numbits = 0
146 self.step = 2
483f2aff 147 elif clk == 0:
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148 # CLK low again, transfer aborted.
149 self.step = 0
150 elif self.step == 2:
483f2aff 151 if data == 0 and clk == 1:
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152 # DATA goes low while CLK is still high, EOI confirmed.
153 self.saved_EOI = True
483f2aff 154 elif clk == 0:
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155 self.step = 3
156 elif self.step == 3:
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157 if self.matched[1]:
158 if clk == 1:
159 # Rising edge on CLK; latch DATA.
160 self.bits |= data << self.numbits
161 elif clk == 0:
162 # Falling edge on CLK; end of bit.
163 self.numbits += 1
164 if self.numbits == 8:
165 self.handle_bits()
166 self.step = 0